Details
| Original language | English |
|---|---|
| Title of host publication | 2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST) |
| Pages | 1-6 |
| Number of pages | 6 |
| ISBN (electronic) | 9781728166872 |
| Publication status | Published - 2020 |
Abstract
In this paper, an operand masking approach is proposed to achieve lower energy consumption using approximate computing techniques in programmable high-performance processors, in this case horizontal and vertical SIMD vector processors for embedded computer vision applications. Contrary to state-of-the-art dedicated approximate arithmetic circuits, this mechanism enables programmable fine-grained accuracy control and switching energy reduction at runtime. An evaluation for a 45 nm ASIC technology shows a total effective energy reduction of up to 4.5% for a horizontal SIMD vector processor architecture executing approximate SIFT image feature extraction for an error-resilient egomotion estimation algorithm.
Keywords
- Approximate Computing, Energy Efficiency, Error-Resilient Applications, Feature Extraction, Processor Architectures
ASJC Scopus subject areas
- Computer Science(all)
- Computer Networks and Communications
- Computer Science(all)
- Hardware and Architecture
- Energy(all)
- Energy Engineering and Power Technology
- Engineering(all)
- Electrical and Electronic Engineering
- Engineering(all)
- Safety, Risk, Reliability and Quality
- Mathematics(all)
- Control and Optimization
Sustainable Development Goals
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2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST). 2020. p. 1-6 9200278.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A Runtime-Reconfigurable Operand Masking Technique for Energy-Efficient Approximate Processor Architectures
AU - Weißbrich, M.
AU - García-Ortiz, A.
AU - Payá-Vayá, G.
N1 - Funding information: This work was partly funded by the German Research Council (DFG) under project number PA 2762/1-1.
PY - 2020
Y1 - 2020
N2 - In this paper, an operand masking approach is proposed to achieve lower energy consumption using approximate computing techniques in programmable high-performance processors, in this case horizontal and vertical SIMD vector processors for embedded computer vision applications. Contrary to state-of-the-art dedicated approximate arithmetic circuits, this mechanism enables programmable fine-grained accuracy control and switching energy reduction at runtime. An evaluation for a 45 nm ASIC technology shows a total effective energy reduction of up to 4.5% for a horizontal SIMD vector processor architecture executing approximate SIFT image feature extraction for an error-resilient egomotion estimation algorithm.
AB - In this paper, an operand masking approach is proposed to achieve lower energy consumption using approximate computing techniques in programmable high-performance processors, in this case horizontal and vertical SIMD vector processors for embedded computer vision applications. Contrary to state-of-the-art dedicated approximate arithmetic circuits, this mechanism enables programmable fine-grained accuracy control and switching energy reduction at runtime. An evaluation for a 45 nm ASIC technology shows a total effective energy reduction of up to 4.5% for a horizontal SIMD vector processor architecture executing approximate SIFT image feature extraction for an error-resilient egomotion estimation algorithm.
KW - Approximate Computing
KW - Energy Efficiency
KW - Error-Resilient Applications
KW - Feature Extraction
KW - Processor Architectures
UR - http://www.scopus.com/inward/record.url?scp=85093862136&partnerID=8YFLogxK
U2 - 10.1109/mocast49295.2020.9200278
DO - 10.1109/mocast49295.2020.9200278
M3 - Conference contribution
SN - 978-1-7281-6688-9
SP - 1
EP - 6
BT - 2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST)
ER -