Details
| Original language | English |
|---|---|
| Pages (from-to) | 1021-1024 |
| Number of pages | 4 |
| Journal | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings |
| Volume | 2 |
| Publication status | Published - 2001 |
| Event | 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing - Salt Lake, UT, United States Duration: 7 May 2001 → 11 May 2001 |
Abstract
A programmable processor architecture for MPEG-4 video is proposed, that can serve as a coprocessor module in MPEG-4 decoder systems. It consists of a 64-bit dual-issue VLIW macroblock engine, a separate RISC core for bitstream parsing and system processing, and an autonomous I/O processor. A separate DSP is used for MPEG audio support. The architecture is fully programmable and supports parallelism on data-, instruction- and thread-level to cope with the high flexibility and processing demands of the MPEG-4 standard. The first implementation will support real-time decoding of MPEG-4 advanced simple profile or of MPEG-4 ACE-profile (CCIR601, single-object). Future designs will add support for object-based MPEG-4 functionalities. The paper focuses on the architecture, instruction set, and performance of the macroblock engine, which operates as an autonomous co-processor and carries most of the workload in MPEG-4 video processing. It has a RISC-based architecture with support for parallel processing of instructions and data. Special instructions are implemented with specific support for video processing.
ASJC Scopus subject areas
- Computer Science(all)
- Software
- Computer Science(all)
- Signal Processing
- Engineering(all)
- Electrical and Electronic Engineering
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In: ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, Vol. 2, 2001, p. 1021-1024.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - A programmable co-processor for MPEG-4 video
AU - Berekovic, M.
AU - Stolberg, H. J.
AU - Pirsch, P.
AU - Runge, H.
PY - 2001
Y1 - 2001
N2 - A programmable processor architecture for MPEG-4 video is proposed, that can serve as a coprocessor module in MPEG-4 decoder systems. It consists of a 64-bit dual-issue VLIW macroblock engine, a separate RISC core for bitstream parsing and system processing, and an autonomous I/O processor. A separate DSP is used for MPEG audio support. The architecture is fully programmable and supports parallelism on data-, instruction- and thread-level to cope with the high flexibility and processing demands of the MPEG-4 standard. The first implementation will support real-time decoding of MPEG-4 advanced simple profile or of MPEG-4 ACE-profile (CCIR601, single-object). Future designs will add support for object-based MPEG-4 functionalities. The paper focuses on the architecture, instruction set, and performance of the macroblock engine, which operates as an autonomous co-processor and carries most of the workload in MPEG-4 video processing. It has a RISC-based architecture with support for parallel processing of instructions and data. Special instructions are implemented with specific support for video processing.
AB - A programmable processor architecture for MPEG-4 video is proposed, that can serve as a coprocessor module in MPEG-4 decoder systems. It consists of a 64-bit dual-issue VLIW macroblock engine, a separate RISC core for bitstream parsing and system processing, and an autonomous I/O processor. A separate DSP is used for MPEG audio support. The architecture is fully programmable and supports parallelism on data-, instruction- and thread-level to cope with the high flexibility and processing demands of the MPEG-4 standard. The first implementation will support real-time decoding of MPEG-4 advanced simple profile or of MPEG-4 ACE-profile (CCIR601, single-object). Future designs will add support for object-based MPEG-4 functionalities. The paper focuses on the architecture, instruction set, and performance of the macroblock engine, which operates as an autonomous co-processor and carries most of the workload in MPEG-4 video processing. It has a RISC-based architecture with support for parallel processing of instructions and data. Special instructions are implemented with specific support for video processing.
UR - http://www.scopus.com/inward/record.url?scp=0034841719&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0034841719
VL - 2
SP - 1021
EP - 1024
JO - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
JF - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
SN - 1520-6149
T2 - 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing
Y2 - 7 May 2001 through 11 May 2001
ER -