Details
| Original language | English |
|---|---|
| Title of host publication | 2007 International Conference on Field Programmable Logic and Applications |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 171-176 |
| Number of pages | 6 |
| ISBN (print) | 978-1-4244-1059-0 |
| Publication status | Published - 12 Nov 2007 |
| Externally published | Yes |
| Event | 2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands Duration: 27 Aug 2007 → 29 Aug 2007 |
Abstract
We describe the application of a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach to a processor model implemented on an FPGA. This technique enables the estimation of the task specific power consumption of the modeled processor, in our case a LEON2, very early during a system design flow, based on the software which will run on it. The FLPA/ILPA model used during our work as well as the test scenarios and the measured results are described. Later, the function block separation and the power consumption modeling are discussed. Finally, the model is validated by benchmarking. The obtained model is promising in the sense that a) its estimations are close (4 % on average) to the measured data, and b) the model structure is similar to that of hardcore processors which is not a trivial result.
ASJC Scopus subject areas
- Computer Science(all)
- Computer Science Applications
- Engineering(all)
- Electrical and Electronic Engineering
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2007 International Conference on Field Programmable Logic and Applications. Institute of Electrical and Electronics Engineers Inc., 2007. p. 171-176 4380643.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A Power Estimation Model for an FPGA-Based Softcore Processor
AU - Zipf, Peter
AU - Hinkelmann, Heiko
AU - Deng, Lei
AU - Glesner, Manfred
AU - Blume, Holger
AU - Noll, Tobias G.
PY - 2007/11/12
Y1 - 2007/11/12
N2 - We describe the application of a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach to a processor model implemented on an FPGA. This technique enables the estimation of the task specific power consumption of the modeled processor, in our case a LEON2, very early during a system design flow, based on the software which will run on it. The FLPA/ILPA model used during our work as well as the test scenarios and the measured results are described. Later, the function block separation and the power consumption modeling are discussed. Finally, the model is validated by benchmarking. The obtained model is promising in the sense that a) its estimations are close (4 % on average) to the measured data, and b) the model structure is similar to that of hardcore processors which is not a trivial result.
AB - We describe the application of a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach to a processor model implemented on an FPGA. This technique enables the estimation of the task specific power consumption of the modeled processor, in our case a LEON2, very early during a system design flow, based on the software which will run on it. The FLPA/ILPA model used during our work as well as the test scenarios and the measured results are described. Later, the function block separation and the power consumption modeling are discussed. Finally, the model is validated by benchmarking. The obtained model is promising in the sense that a) its estimations are close (4 % on average) to the measured data, and b) the model structure is similar to that of hardcore processors which is not a trivial result.
UR - http://www.scopus.com/inward/record.url?scp=48149110001&partnerID=8YFLogxK
U2 - 10.1109/FPL.2007.4380643
DO - 10.1109/FPL.2007.4380643
M3 - Conference contribution
AN - SCOPUS:48149110001
SN - 978-1-4244-1059-0
SP - 171
EP - 176
BT - 2007 International Conference on Field Programmable Logic and Applications
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2007 International Conference on Field Programmable Logic and Applications, FPL
Y2 - 27 August 2007 through 29 August 2007
ER -