Details
| Original language | English |
|---|---|
| Title of host publication | ASAP08, Conference Proceedings - IEEE 19th International Conference on Application-Specific Systems, Architectures and Processors |
| Pages | 144-149 |
| Number of pages | 6 |
| Publication status | Published - 2008 |
| Event | ASAP08 - IEEE 19th International Conference on Application-Specific Systems, Architectures and Processors - Leuven, Belgium Duration: 2 Jul 2008 → 4 Jul 2008 |
Publication series
| Name | Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors |
|---|---|
| ISSN (Print) | 1063-6862 |
Abstract
This paper presents a dedicated parallel hardware architecture for fast connected component labeling. Both, label generation and merging of equivalent labels are accelerated. Label generation is performed for four pixels in parallel. A special linked list based approach for fast label merging is proposed. This results in a compact implementation and shorter processing times compared to published implementations. For prototyping and evaluation purposes, the hardware architecture was integrated into an FPGA-based modular coprocessor architecture. A binary D1 test image is labeled in 1.74 ms on a Virtex-II Pro FPGA running at 140 MHz. Moreover, the architecture can be easily integrated into embedded image processing systems.
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Computer Science(all)
- Computer Networks and Communications
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ASAP08, Conference Proceedings - IEEE 19th International Conference on Application-Specific Systems, Architectures and Processors. 2008. p. 144-149 4580169 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A parallel hardware architecture for connected component labeling based on fast label merging
AU - Flatt, Holger
AU - Blume, Steffen
AU - Hesselbarth, Sebastian
AU - Schünemann, Torsten
AU - Pirsch, Peter
PY - 2008
Y1 - 2008
N2 - This paper presents a dedicated parallel hardware architecture for fast connected component labeling. Both, label generation and merging of equivalent labels are accelerated. Label generation is performed for four pixels in parallel. A special linked list based approach for fast label merging is proposed. This results in a compact implementation and shorter processing times compared to published implementations. For prototyping and evaluation purposes, the hardware architecture was integrated into an FPGA-based modular coprocessor architecture. A binary D1 test image is labeled in 1.74 ms on a Virtex-II Pro FPGA running at 140 MHz. Moreover, the architecture can be easily integrated into embedded image processing systems.
AB - This paper presents a dedicated parallel hardware architecture for fast connected component labeling. Both, label generation and merging of equivalent labels are accelerated. Label generation is performed for four pixels in parallel. A special linked list based approach for fast label merging is proposed. This results in a compact implementation and shorter processing times compared to published implementations. For prototyping and evaluation purposes, the hardware architecture was integrated into an FPGA-based modular coprocessor architecture. A binary D1 test image is labeled in 1.74 ms on a Virtex-II Pro FPGA running at 140 MHz. Moreover, the architecture can be easily integrated into embedded image processing systems.
UR - http://www.scopus.com/inward/record.url?scp=51649094584&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2008.4580169
DO - 10.1109/ASAP.2008.4580169
M3 - Conference contribution
AN - SCOPUS:51649094584
SN - 9781424418985
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 144
EP - 149
BT - ASAP08, Conference Proceedings - IEEE 19th International Conference on Application-Specific Systems, Architectures and Processors
T2 - ASAP08 - IEEE 19th International Conference on Application-Specific Systems, Architectures and Processors
Y2 - 2 July 2008 through 4 July 2008
ER -