Details
| Original language | English |
|---|---|
| Title of host publication | IEEE ISCAS 2023 |
| Subtitle of host publication | Symposium Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (electronic) | 9781665451093 |
| ISBN (print) | 978-1-6654-5110-9 |
| Publication status | Published - 2023 |
| Event | 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 - Monterey, United States Duration: 21 May 2023 → 25 May 2023 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Volume | 2023-May |
| ISSN (Print) | 0271-4310 |
Abstract
This paper presents a new architecture as well as a compensation method for discrete-time (DT) noise-canceling SMASH (NC-SMASH) bandpass delta-sigma modula-tors (BP-ΔΣMs). The proposed method relaxes timing constraints on the feedback path by one clock cycle, which in turn relaxes the timing constraints on the adder in front of the quantizer, and the digital adder for the SMASH architecture. In SMASH architectures, this relaxed timing enables an NC analog-to-digital converter (ADC) architecture. Unlike state-of-the-art solutions, which require an analog unit delay at the ADC's input to achieve these relaxed requirements, the presented bandpass approach renders this analog delay and the respective input capacitor unnecessary. In a respective circuit implementation this significantly reduces the area and power consumption. The proposed compensation method allows the designer to choose between a non-delayed input and an elimination of the input signal component inside the loop filter, which would require a delayed input path.
Keywords
- analog-to-digital converter (ADC), bandpass, delta-sigma modulators, discrete-time (DT), noise-canceling sturdy multistage noise-shaping (NC-SMASH)
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
Cite this
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IEEE ISCAS 2023: Symposium Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2023-May).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs
AU - Flemming, Jesko
AU - Wicht, Bernhard
AU - Witte, Pascal
PY - 2023
Y1 - 2023
N2 - This paper presents a new architecture as well as a compensation method for discrete-time (DT) noise-canceling SMASH (NC-SMASH) bandpass delta-sigma modula-tors (BP-ΔΣMs). The proposed method relaxes timing constraints on the feedback path by one clock cycle, which in turn relaxes the timing constraints on the adder in front of the quantizer, and the digital adder for the SMASH architecture. In SMASH architectures, this relaxed timing enables an NC analog-to-digital converter (ADC) architecture. Unlike state-of-the-art solutions, which require an analog unit delay at the ADC's input to achieve these relaxed requirements, the presented bandpass approach renders this analog delay and the respective input capacitor unnecessary. In a respective circuit implementation this significantly reduces the area and power consumption. The proposed compensation method allows the designer to choose between a non-delayed input and an elimination of the input signal component inside the loop filter, which would require a delayed input path.
AB - This paper presents a new architecture as well as a compensation method for discrete-time (DT) noise-canceling SMASH (NC-SMASH) bandpass delta-sigma modula-tors (BP-ΔΣMs). The proposed method relaxes timing constraints on the feedback path by one clock cycle, which in turn relaxes the timing constraints on the adder in front of the quantizer, and the digital adder for the SMASH architecture. In SMASH architectures, this relaxed timing enables an NC analog-to-digital converter (ADC) architecture. Unlike state-of-the-art solutions, which require an analog unit delay at the ADC's input to achieve these relaxed requirements, the presented bandpass approach renders this analog delay and the respective input capacitor unnecessary. In a respective circuit implementation this significantly reduces the area and power consumption. The proposed compensation method allows the designer to choose between a non-delayed input and an elimination of the input signal component inside the loop filter, which would require a delayed input path.
KW - analog-to-digital converter (ADC)
KW - bandpass
KW - delta-sigma modulators
KW - discrete-time (DT)
KW - noise-canceling sturdy multistage noise-shaping (NC-SMASH)
UR - http://www.scopus.com/inward/record.url?scp=85167652442&partnerID=8YFLogxK
U2 - 10.1109/ISCAS46773.2023.10181385
DO - 10.1109/ISCAS46773.2023.10181385
M3 - Conference contribution
AN - SCOPUS:85167652442
SN - 978-1-6654-5110-9
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE ISCAS 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Y2 - 21 May 2023 through 25 May 2023
ER -