A multimedia RISC core for efficient bitstream parsing and VLD

Research output: Contribution to journal › Conference article › Research › peer review

Authors

  • Mladen Berekovic
  • Gerald Meyer
  • Yong Guo
  • Peter Pirsch

Research Organisations

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Details

Original languageEnglish
Pages (from-to)131-141
Number of pages11
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume3311
Publication statusPublished - 26 Mar 1998
EventMultimedia Hardware Architectures 1998 - San Jose, CA, United States
Duration: 29 Jan 1998 → 30 Jan 1998

Abstract

Demand for highly flexible and fast implementations for bitstream parsing and variable-length-decoding (VLD) arises, if applications are targeted that shall support either MPEG-4 or multiple standards like MPEG-2, H.263 or Dolby AC3. The paper shows that especially today's multimedia oriented RISC processors incorporating multiple parallel arithmetic units are slowed down by these kind of bit-level operations. Therefore, a new architecture is proposed, that adds function specific blocks into the data path of a RISC processor, that are highly adapted to the processing of variable-length coded bitstream data. The increased functional complexity of basic instructions results in a significant speedup over software implementations on standard RISC processors. Two typical functions, that are frequently used in bitstream parsing, ShowBits (reading a certain number of bits) and GetBits (reading and removing a certain number of bits from the incoming bitstream), are executed in a single clock-cycle with a 64 bit rotator circuit. Constant input-rate VLD of one, two or four bits per clock-cycle can be implemented using internal RAM. Lookup-tables can be used for word-parallel decoding and VLC. Optionally memory entries can be saved using content addressable memories (CAMs) in addition to a data RAM. The proposed architecture has been implemented as a functional extension to an existing RISC core with additional 9k gates of logic, 8k RAM and an interface to a CAM. Synthesis results show an estimate of 160 MHz achievable clock frequency using a 0.35 μ technology. The resulting performance is sufficient for MPEG-2 HDTV or MPEG-4 applications.

Keywords

    Bitstream parsing, Core, Huffman Codes, MPEG-4, Programmable, Reversible codes, RISC, VLC, VLD

ASJC Scopus subject areas

Cite this

A multimedia RISC core for efficient bitstream parsing and VLD. / Berekovic, Mladen; Meyer, Gerald; Guo, Yong et al.
In: Proceedings of SPIE - The International Society for Optical Engineering, Vol. 3311, 26.03.1998, p. 131-141.

Research output: Contribution to journal › Conference article › Research › peer review

Berekovic, M, Meyer, G, Guo, Y & Pirsch, P 1998, 'A multimedia RISC core for efficient bitstream parsing and VLD', Proceedings of SPIE - The International Society for Optical Engineering, vol. 3311, pp. 131-141. https://doi.org/10.1117/12.304665
Berekovic, M., Meyer, G., Guo, Y., & Pirsch, P. (1998). A multimedia RISC core for efficient bitstream parsing and VLD. Proceedings of SPIE - The International Society for Optical Engineering, 3311, 131-141. https://doi.org/10.1117/12.304665
Berekovic M, Meyer G, Guo Y, Pirsch P. A multimedia RISC core for efficient bitstream parsing and VLD. Proceedings of SPIE - The International Society for Optical Engineering. 1998 Mar 26;3311:131-141. doi: 10.1117/12.304665
Berekovic, Mladen ; Meyer, Gerald ; Guo, Yong et al. / A multimedia RISC core for efficient bitstream parsing and VLD. In: Proceedings of SPIE - The International Society for Optical Engineering. 1998 ; Vol. 3311. pp. 131-141.
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