Details
Original language | English |
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Title of host publication | Embedded Computer Systems |
Subtitle of host publication | Architectures, Modeling, and Simulation |
Publisher | Springer Verlag |
Pages | 241-250 |
Number of pages | 10 |
ISBN (print) | 9783540736226 |
Publication status | Published - 2007 |
Event | 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2007 - Samos, Greece Duration: 16 Jul 2007 → 19 Jul 2007 |
Publication series
Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
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Volume | 4599 LNCS |
ISSN (Print) | 0302-9743 |
ISSN (electronic) | 1611-3349 |
Abstract
This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.
ASJC Scopus subject areas
- Mathematics(all)
- Theoretical Computer Science
- Computer Science(all)
- General Computer Science
Cite this
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Embedded Computer Systems: Architectures, Modeling, and Simulation . Springer Verlag, 2007. p. 241-250 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4599 LNCS).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A modular coprocessor architecture for embedded real-time image and video signal processing
AU - Flatt, Holger
AU - Hesselbarth, Sebastian
AU - Flügel, Sebastian
AU - Pirsch, Peter
PY - 2007
Y1 - 2007
N2 - This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.
AB - This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.
UR - http://www.scopus.com/inward/record.url?scp=38149102303&partnerID=8YFLogxK
U2 - 10.1007/978-3-540-73625-7_26
DO - 10.1007/978-3-540-73625-7_26
M3 - Conference contribution
AN - SCOPUS:38149102303
SN - 9783540736226
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 241
EP - 250
BT - Embedded Computer Systems
PB - Springer Verlag
T2 - 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2007
Y2 - 16 July 2007 through 19 July 2007
ER -