A modular coprocessor architecture for embedded real-time image and video signal processing

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Authors

  • Holger Flatt
  • Sebastian Hesselbarth
  • Sebastian Flügel
  • Peter Pirsch

Research Organisations

View graph of relations

Details

Original languageEnglish
Title of host publicationEmbedded Computer Systems
Subtitle of host publicationArchitectures, Modeling, and Simulation
PublisherSpringer Verlag
Pages241-250
Number of pages10
ISBN (print)9783540736226
Publication statusPublished - 2007
Event7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2007 - Samos, Greece
Duration: 16 Jul 200719 Jul 2007

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4599 LNCS
ISSN (Print)0302-9743
ISSN (electronic)1611-3349

Abstract

This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.

ASJC Scopus subject areas

Cite this

A modular coprocessor architecture for embedded real-time image and video signal processing. / Flatt, Holger; Hesselbarth, Sebastian; Flügel, Sebastian et al.
Embedded Computer Systems: Architectures, Modeling, and Simulation . Springer Verlag, 2007. p. 241-250 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4599 LNCS).

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Flatt, H, Hesselbarth, S, Flügel, S & Pirsch, P 2007, A modular coprocessor architecture for embedded real-time image and video signal processing. in Embedded Computer Systems: Architectures, Modeling, and Simulation . Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4599 LNCS, Springer Verlag, pp. 241-250, 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2007, Samos, Greece, 16 Jul 2007. https://doi.org/10.1007/978-3-540-73625-7_26
Flatt, H., Hesselbarth, S., Flügel, S., & Pirsch, P. (2007). A modular coprocessor architecture for embedded real-time image and video signal processing. In Embedded Computer Systems: Architectures, Modeling, and Simulation (pp. 241-250). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4599 LNCS). Springer Verlag. https://doi.org/10.1007/978-3-540-73625-7_26
Flatt H, Hesselbarth S, Flügel S, Pirsch P. A modular coprocessor architecture for embedded real-time image and video signal processing. In Embedded Computer Systems: Architectures, Modeling, and Simulation . Springer Verlag. 2007. p. 241-250. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-73625-7_26
Flatt, Holger ; Hesselbarth, Sebastian ; Flügel, Sebastian et al. / A modular coprocessor architecture for embedded real-time image and video signal processing. Embedded Computer Systems: Architectures, Modeling, and Simulation . Springer Verlag, 2007. pp. 241-250 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
Download
@inproceedings{ee3d524302a443fba763fb17434aacdd,
title = "A modular coprocessor architecture for embedded real-time image and video signal processing",
abstract = "This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.",
author = "Holger Flatt and Sebastian Hesselbarth and Sebastian Fl{\"u}gel and Peter Pirsch",
year = "2007",
doi = "10.1007/978-3-540-73625-7_26",
language = "English",
isbn = "9783540736226",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "241--250",
booktitle = "Embedded Computer Systems",
address = "Germany",
note = "7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2007 ; Conference date: 16-07-2007 Through 19-07-2007",

}

Download

TY - GEN

T1 - A modular coprocessor architecture for embedded real-time image and video signal processing

AU - Flatt, Holger

AU - Hesselbarth, Sebastian

AU - Flügel, Sebastian

AU - Pirsch, Peter

PY - 2007

Y1 - 2007

N2 - This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.

AB - This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.

UR - http://www.scopus.com/inward/record.url?scp=38149102303&partnerID=8YFLogxK

U2 - 10.1007/978-3-540-73625-7_26

DO - 10.1007/978-3-540-73625-7_26

M3 - Conference contribution

AN - SCOPUS:38149102303

SN - 9783540736226

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 241

EP - 250

BT - Embedded Computer Systems

PB - Springer Verlag

T2 - 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2007

Y2 - 16 July 2007 through 19 July 2007

ER -