Details
| Original language | English |
|---|---|
| Title of host publication | BMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop |
| Pages | 19-24 |
| Number of pages | 6 |
| Publication status | Published - 2005 |
| Event | BMAS 2005 - 2005 IEEE International Behavioral Modeling and Simulation Workshop - San Jose, CA, United States Duration: 22 Sept 2005 → 23 Sept 2005 |
Publication series
| Name | BMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop |
|---|---|
| Volume | 2005 |
Abstract
Switching of power stages in smart power ICs, which drive an inductive load, turns on parasitic bipolar transistors and injects minority carriers into the substrate, which can affect the functionality of the chip. In order to evaluate protection measures, these parasitic transistors have to be included into a post layout simulation. In this paper, we present a methodology for automatically generating Verilog-A models for these parasites from layout data. As these models have to account for high injection effects and a distributed current flow, the convergence behavior of this models will be worse than that of classical bipolar models. We found a reasonable trade-off between convergence behavior and accuracy of the model.
ASJC Scopus subject areas
- Engineering(all)
- General Engineering
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BMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop. 2005. p. 19-24 1518181 (BMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop; Vol. 2005).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A methodology for modeling lateral parasitic transistors in smart power ICs
AU - Oehmen, Joerg
AU - Hedrich, Lars
AU - Olbrich, Markus
AU - Barke, Erich
PY - 2005
Y1 - 2005
N2 - Switching of power stages in smart power ICs, which drive an inductive load, turns on parasitic bipolar transistors and injects minority carriers into the substrate, which can affect the functionality of the chip. In order to evaluate protection measures, these parasitic transistors have to be included into a post layout simulation. In this paper, we present a methodology for automatically generating Verilog-A models for these parasites from layout data. As these models have to account for high injection effects and a distributed current flow, the convergence behavior of this models will be worse than that of classical bipolar models. We found a reasonable trade-off between convergence behavior and accuracy of the model.
AB - Switching of power stages in smart power ICs, which drive an inductive load, turns on parasitic bipolar transistors and injects minority carriers into the substrate, which can affect the functionality of the chip. In order to evaluate protection measures, these parasitic transistors have to be included into a post layout simulation. In this paper, we present a methodology for automatically generating Verilog-A models for these parasites from layout data. As these models have to account for high injection effects and a distributed current flow, the convergence behavior of this models will be worse than that of classical bipolar models. We found a reasonable trade-off between convergence behavior and accuracy of the model.
UR - http://www.scopus.com/inward/record.url?scp=33746791952&partnerID=8YFLogxK
U2 - 10.1109/BMAS.2005.1518181
DO - 10.1109/BMAS.2005.1518181
M3 - Conference contribution
AN - SCOPUS:33746791952
SN - 078039352X
SN - 9780780393523
T3 - BMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop
SP - 19
EP - 24
BT - BMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop
T2 - BMAS 2005 - 2005 IEEE International Behavioral Modeling and Simulation Workshop
Y2 - 22 September 2005 through 23 September 2005
ER -