Details
| Original language | English |
|---|---|
| Article number | 389633 |
| Pages (from-to) | II413-II416 |
| Journal | Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) |
| Volume | 2 |
| Publication status | Published - 1994 |
| Event | 1994 IEEE International Conference on Acoustics, Speech and Signal Processing. Part 2 (of 6) - Adelaide, Australia Duration: 19 Apr 1994 → 22 Apr 1994 |
Abstract
In this paper a heterogenous processor architecture for video coding applications based on hybrid coding schemes is proposed. To support high computational power and architectural flexibility, the processor consists of function oriented and programmable modules. The key components of the architecture are a RISC core which performs control tasks and module synchronisation, a programmable module for tasks like DCT, quantization and filtering and a function oriented blockmatching module for motion estimation. Applying a 0.6 micron CMOS process, a single chip video codec for CIF-30 Hz video signals can be implemented. For higher video source rates several processors can be combined to a multiprocessor system.
ASJC Scopus subject areas
- Computer Science(all)
- Software
- Computer Science(all)
- Signal Processing
- Engineering(all)
- Electrical and Electronic Engineering
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In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Vol. 2, 389633, 1994, p. II413-II416.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - A hierarchical multiprocessor architecture based on heterogeneous processors for video coding applications
AU - Gehrke, W.
AU - Hoffer, R.
AU - Pirsch, P.
N1 - Funding Information: This work is supported by the Corporate Research and De- velopment Siemens AG, Germany.
PY - 1994
Y1 - 1994
N2 - In this paper a heterogenous processor architecture for video coding applications based on hybrid coding schemes is proposed. To support high computational power and architectural flexibility, the processor consists of function oriented and programmable modules. The key components of the architecture are a RISC core which performs control tasks and module synchronisation, a programmable module for tasks like DCT, quantization and filtering and a function oriented blockmatching module for motion estimation. Applying a 0.6 micron CMOS process, a single chip video codec for CIF-30 Hz video signals can be implemented. For higher video source rates several processors can be combined to a multiprocessor system.
AB - In this paper a heterogenous processor architecture for video coding applications based on hybrid coding schemes is proposed. To support high computational power and architectural flexibility, the processor consists of function oriented and programmable modules. The key components of the architecture are a RISC core which performs control tasks and module synchronisation, a programmable module for tasks like DCT, quantization and filtering and a function oriented blockmatching module for motion estimation. Applying a 0.6 micron CMOS process, a single chip video codec for CIF-30 Hz video signals can be implemented. For higher video source rates several processors can be combined to a multiprocessor system.
UR - http://www.scopus.com/inward/record.url?scp=9344263897&partnerID=8YFLogxK
U2 - 10.1109/ICASSP.1994.389633
DO - 10.1109/ICASSP.1994.389633
M3 - Conference article
AN - SCOPUS:9344263897
VL - 2
SP - II413-II416
JO - Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)
JF - Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)
SN - 1520-6149
M1 - 389633
T2 - 1994 IEEE International Conference on Acoustics, Speech and Signal Processing. Part 2 (of 6)
Y2 - 19 April 1994 through 22 April 1994
ER -