Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (electronic) | 9798350351927 |
| ISBN (print) | 979-8-3503-5193-4 |
| Publication status | Published - 2 Jul 2024 |
| Event | 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024 - Volos, Greece Duration: 2 Jul 2024 → 5 Jul 2024 |
Publication series
| Name | International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design |
|---|---|
| ISSN (electronic) | 2575-4890 |
Abstract
This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.
Keywords
- analog-to-digital converter, delta-sigma modulator, efficient, linearization
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Electrical and Electronic Engineering
- Engineering(all)
- Safety, Risk, Reliability and Quality
- Mathematics(all)
- Modelling and Simulation
- Physics and Astronomy(all)
- Instrumentation
Cite this
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Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs
AU - Flemming, Jesko
AU - Rogge, Timon
AU - Wicht, Bernhard
AU - Witte, Pascal
N1 - Publisher Copyright: © 2024 IEEE.
PY - 2024/7/2
Y1 - 2024/7/2
N2 - This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.
AB - This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.
KW - analog-to-digital converter
KW - delta-sigma modulator
KW - efficient
KW - linearization
UR - http://www.scopus.com/inward/record.url?scp=85211899115&partnerID=8YFLogxK
U2 - 10.1109/SMACD61181.2024.10745378
DO - 10.1109/SMACD61181.2024.10745378
M3 - Conference contribution
AN - SCOPUS:85211899115
SN - 979-8-3503-5193-4
T3 - International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
BT - Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024
Y2 - 2 July 2024 through 5 July 2024
ER -