A gate sizing method for glitch power reduction.

Research output: Contribution to conference › Paper › Research › peer review

Authors

  • Lei Wang
  • Markus Olbrich
  • Erich Barke
  • Thomas Büchner
  • Markus Bühler
  • Philipp V. Panitz

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Details

Original languageUndefined/Unknown
Pages24-29
Publication statusPublished - 2011

Cite this

A gate sizing method for glitch power reduction. / Wang, Lei; Olbrich, Markus; Barke, Erich et al.
2011. 24-29.

Research output: Contribution to conference › Paper › Research › peer review

Wang, L, Olbrich, M, Barke, E, Büchner, T, Bühler, M & Panitz, PV 2011, 'A gate sizing method for glitch power reduction.', pp. 24-29. https://doi.org/10.1109/SOCC.2011.6085070
Wang, L., Olbrich, M., Barke, E., Büchner, T., Bühler, M., & Panitz, P. V. (2011). A gate sizing method for glitch power reduction.. 24-29. https://doi.org/10.1109/SOCC.2011.6085070
Wang L, Olbrich M, Barke E, Büchner T, Bühler M, Panitz PV. A gate sizing method for glitch power reduction.. 2011. doi: 10.1109/SOCC.2011.6085070
Wang, Lei ; Olbrich, Markus ; Barke, Erich et al. / A gate sizing method for glitch power reduction.
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AU - Bühler, Markus

AU - Panitz, Philipp V.

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