Details
| Original language | English |
|---|---|
| Title of host publication | 2024 IEEE International Solid-State Circuits Conference |
| Subtitle of host publication | ISSCC |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 514-516 |
| Number of pages | 3 |
| ISBN (electronic) | 9798350306200 |
| ISBN (print) | 979-8-3503-0621-7 |
| Publication status | Published - 2024 |
| Event | 2024 IEEE International Solid-State Circuits Conference, ISSCC 2024 - San Francisco, United States Duration: 18 Feb 2024 → 22 Feb 2024 |
Publication series
| Name | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
|---|---|
| ISSN (Print) | 0193-6530 |
Abstract
Grid-powered devices such as desktop computers, displays and TVs, industrial power supplies, and 5G infrastructure are experiencing an increasing demand for higher power efficiency and density. Despite the moderate power levels (below 100W), these devices collectively consume over 10TWh annually. High energy efficiency is key to reducing global energy usage. Flatter screens and smaller desktop computers call for more compact power interfaces. Both goals favor GaN technology due to its low-loss highfrequency switching capability. For grid-powered applications, a power-factor correction (PFC) stage minimizes the reactive power and regulates the 120/230V AC line voltage to a DC voltage VHV = 200/400V, as shown in Fig. 31.10.1 (top). A subsequent DC/DC converter converts VHV to typically 12 to 48V. Conventional PFC converters use a boost stage combined with a full-bridge rectifier, illustrated in Fig. 31.10.1 (middle left). Such a topology shows limited efficiency with several diodes in the power path [1]. The bridgeless totem-pole PFC converter (TPPFC), Fig. 31.10.1 (middle right), replaces the diodes with transistors significantly reducing losses. Transistors MRH and MRL are switched in sync with the line frequency of 50/60 Hz, acting as a rectifier for the AC input. Due to the low switching frequency, they can be implemented using any transistor type with low on-state resistance. During the positive line cycle (Fig. 31.10.1 middle right), ML acts as the active switch to energize the inductor L during the duty cycle D. MH is the synchronous rectifier guiding the current to the output during the freewheeling phase (1-D). When the line voltage changes polarity, ML and MH exchange roles. Favorable for lower output powers, the presented TPPFC employs DCM regulation [1]. GaN-FETs, inherently free of a body diode structure (see cross-section in Fig. 31.10.2), are ideal for efficient hard-switching of MH and ML in the TPPFC, where use of silicon transistors is not feasible due to reverse-recovery charge related losses.
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Engineering(all)
- Electrical and Electronic Engineering
Sustainable Development Goals
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2024 IEEE International Solid-State Circuits Conference: ISSCC. Institute of Electrical and Electronics Engineers Inc., 2024. p. 514-516 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A Fully integrated 500V, 6.25MHz GaN-IC for Totem-Pole PFC Off-Line Power Conversion
AU - Deneke, Niklas
AU - Wicht, Bernhard
PY - 2024
Y1 - 2024
N2 - Grid-powered devices such as desktop computers, displays and TVs, industrial power supplies, and 5G infrastructure are experiencing an increasing demand for higher power efficiency and density. Despite the moderate power levels (below 100W), these devices collectively consume over 10TWh annually. High energy efficiency is key to reducing global energy usage. Flatter screens and smaller desktop computers call for more compact power interfaces. Both goals favor GaN technology due to its low-loss highfrequency switching capability. For grid-powered applications, a power-factor correction (PFC) stage minimizes the reactive power and regulates the 120/230V AC line voltage to a DC voltage VHV = 200/400V, as shown in Fig. 31.10.1 (top). A subsequent DC/DC converter converts VHV to typically 12 to 48V. Conventional PFC converters use a boost stage combined with a full-bridge rectifier, illustrated in Fig. 31.10.1 (middle left). Such a topology shows limited efficiency with several diodes in the power path [1]. The bridgeless totem-pole PFC converter (TPPFC), Fig. 31.10.1 (middle right), replaces the diodes with transistors significantly reducing losses. Transistors MRH and MRL are switched in sync with the line frequency of 50/60 Hz, acting as a rectifier for the AC input. Due to the low switching frequency, they can be implemented using any transistor type with low on-state resistance. During the positive line cycle (Fig. 31.10.1 middle right), ML acts as the active switch to energize the inductor L during the duty cycle D. MH is the synchronous rectifier guiding the current to the output during the freewheeling phase (1-D). When the line voltage changes polarity, ML and MH exchange roles. Favorable for lower output powers, the presented TPPFC employs DCM regulation [1]. GaN-FETs, inherently free of a body diode structure (see cross-section in Fig. 31.10.2), are ideal for efficient hard-switching of MH and ML in the TPPFC, where use of silicon transistors is not feasible due to reverse-recovery charge related losses.
AB - Grid-powered devices such as desktop computers, displays and TVs, industrial power supplies, and 5G infrastructure are experiencing an increasing demand for higher power efficiency and density. Despite the moderate power levels (below 100W), these devices collectively consume over 10TWh annually. High energy efficiency is key to reducing global energy usage. Flatter screens and smaller desktop computers call for more compact power interfaces. Both goals favor GaN technology due to its low-loss highfrequency switching capability. For grid-powered applications, a power-factor correction (PFC) stage minimizes the reactive power and regulates the 120/230V AC line voltage to a DC voltage VHV = 200/400V, as shown in Fig. 31.10.1 (top). A subsequent DC/DC converter converts VHV to typically 12 to 48V. Conventional PFC converters use a boost stage combined with a full-bridge rectifier, illustrated in Fig. 31.10.1 (middle left). Such a topology shows limited efficiency with several diodes in the power path [1]. The bridgeless totem-pole PFC converter (TPPFC), Fig. 31.10.1 (middle right), replaces the diodes with transistors significantly reducing losses. Transistors MRH and MRL are switched in sync with the line frequency of 50/60 Hz, acting as a rectifier for the AC input. Due to the low switching frequency, they can be implemented using any transistor type with low on-state resistance. During the positive line cycle (Fig. 31.10.1 middle right), ML acts as the active switch to energize the inductor L during the duty cycle D. MH is the synchronous rectifier guiding the current to the output during the freewheeling phase (1-D). When the line voltage changes polarity, ML and MH exchange roles. Favorable for lower output powers, the presented TPPFC employs DCM regulation [1]. GaN-FETs, inherently free of a body diode structure (see cross-section in Fig. 31.10.2), are ideal for efficient hard-switching of MH and ML in the TPPFC, where use of silicon transistors is not feasible due to reverse-recovery charge related losses.
UR - http://www.scopus.com/inward/record.url?scp=85188115077&partnerID=8YFLogxK
U2 - 10.1109/ISSCC49657.2024.10454437
DO - 10.1109/ISSCC49657.2024.10454437
M3 - Conference contribution
AN - SCOPUS:85188115077
SN - 979-8-3503-0621-7
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 514
EP - 516
BT - 2024 IEEE International Solid-State Circuits Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
Y2 - 18 February 2024 through 22 February 2024
ER -