Details
| Original language | English |
|---|---|
| Title of host publication | ICECS 2002 |
| Subtitle of host publication | 9th IEEE International Conference on Electronics, Circuits and Systems |
| Pages | 1063-1066 |
| Number of pages | 4 |
| Publication status | Published - 2002 |
| Event | 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002 - Dubrovnik, Croatia Duration: 15 Sept 2002 → 18 Sept 2002 |
Publication series
| Name | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
|---|---|
| Volume | 3 |
Abstract
This paper introduces a video encoder architecture for real-time MPEG-2 Main Profile at Main Level (MP@ML) encoding. It combines a programmable CPU for controlling with a fully configurable, but dedicated compression core. Therefore the encoder architecture offers a great processing flexibility at a high computational performance. One focal point of the paper is the motion estimation unit of the compression core that employs a highly efficient recursive block-matching motion estimation algorithm. To guarantee full memory bandwidth utilization the number of candidate blocks used for the block-matching process can be varied. The compression core was implemented in a 0.18pm 5 ML CMOS technology to run at 54 MHz. The architecture was thoroughly verified using hardware/software co-simulation.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
Cite this
- Standard
- Harvard
- Apa
- Vancouver
- BibTeX
- RIS
ICECS 2002 : 9th IEEE International Conference on Electronics, Circuits and Systems. 2002. p. 1063-1066 1046434 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A flexible, fully configurable architecture for MPEG-2 video encoding
AU - Jachalsky, J.
AU - Wahle, M.
AU - Pirsch, P.
AU - Gehrke, W.
PY - 2002
Y1 - 2002
N2 - This paper introduces a video encoder architecture for real-time MPEG-2 Main Profile at Main Level (MP@ML) encoding. It combines a programmable CPU for controlling with a fully configurable, but dedicated compression core. Therefore the encoder architecture offers a great processing flexibility at a high computational performance. One focal point of the paper is the motion estimation unit of the compression core that employs a highly efficient recursive block-matching motion estimation algorithm. To guarantee full memory bandwidth utilization the number of candidate blocks used for the block-matching process can be varied. The compression core was implemented in a 0.18pm 5 ML CMOS technology to run at 54 MHz. The architecture was thoroughly verified using hardware/software co-simulation.
AB - This paper introduces a video encoder architecture for real-time MPEG-2 Main Profile at Main Level (MP@ML) encoding. It combines a programmable CPU for controlling with a fully configurable, but dedicated compression core. Therefore the encoder architecture offers a great processing flexibility at a high computational performance. One focal point of the paper is the motion estimation unit of the compression core that employs a highly efficient recursive block-matching motion estimation algorithm. To guarantee full memory bandwidth utilization the number of candidate blocks used for the block-matching process can be varied. The compression core was implemented in a 0.18pm 5 ML CMOS technology to run at 54 MHz. The architecture was thoroughly verified using hardware/software co-simulation.
UR - http://www.scopus.com/inward/record.url?scp=77956443131&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2002.1046434
DO - 10.1109/ICECS.2002.1046434
M3 - Conference contribution
AN - SCOPUS:77956443131
SN - 0780375963
SN - 9780780375963
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 1063
EP - 1066
BT - ICECS 2002
T2 - 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002
Y2 - 15 September 2002 through 18 September 2002
ER -