Details
| Original language | English |
|---|---|
| Title of host publication | 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1-6 |
| Number of pages | 6 |
| ISBN (electronic) | 9781509064625 |
| Publication status | Published - 13 Nov 2017 |
| Event | 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017 - Thessaloniki, Greece Duration: 25 Sept 2017 → 27 Sept 2017 |
Abstract
The demands of high-speed and power-efficient systems have resulted into the emergence of the approximate computing. Existing approximate circuits as well as stochastic techniques have shown promising advances in improving various figures of merit. However, a through fair comparison of arithmetic units still remains an issue which has not been studied. This paper reviews the prerequisites for a fair comparison of approximate arithmetic units. As one of the key components of arithmetic circuits, adders are the focus of this paper. For the first time in this paper, approximate and exact adders are studied together in the stochastic regime. Simulation results show that both the equal segmentation adder (ESA) and the error tolerant adder type II (ETAII) outperform exact adders working stochastically, if and only if the right configuration and sub-adder architectures are chosen. Otherwise, there is no reason to use the aforementioned architectures. In all, considering the cost-error trade-off, Lower-part OR adder (LOA) has the best behavior in the stochastic regime.
ASJC Scopus subject areas
- Mathematics(all)
- Modelling and Simulation
- Computer Science(all)
- Computer Networks and Communications
- Computer Science(all)
- Hardware and Architecture
- Energy(all)
- Energy Engineering and Power Technology
- Engineering(all)
- Electrical and Electronic Engineering
- Mathematics(all)
- Control and Optimization
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2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-6.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A fair comparison of adders in stochastic regime
AU - Najafi, Ardalan
AU - Weißbrich, Moritz
AU - Payá Vayá, Guillermo
AU - Garcia-Ortiz, Alberto
N1 - Funding Information: This work is funded by the German Research Foundation (DFG) project GA 763/4-1. Publisher Copyright: © 2017 IEEE. Copyright: Copyright 2018 Elsevier B.V., All rights reserved.
PY - 2017/11/13
Y1 - 2017/11/13
N2 - The demands of high-speed and power-efficient systems have resulted into the emergence of the approximate computing. Existing approximate circuits as well as stochastic techniques have shown promising advances in improving various figures of merit. However, a through fair comparison of arithmetic units still remains an issue which has not been studied. This paper reviews the prerequisites for a fair comparison of approximate arithmetic units. As one of the key components of arithmetic circuits, adders are the focus of this paper. For the first time in this paper, approximate and exact adders are studied together in the stochastic regime. Simulation results show that both the equal segmentation adder (ESA) and the error tolerant adder type II (ETAII) outperform exact adders working stochastically, if and only if the right configuration and sub-adder architectures are chosen. Otherwise, there is no reason to use the aforementioned architectures. In all, considering the cost-error trade-off, Lower-part OR adder (LOA) has the best behavior in the stochastic regime.
AB - The demands of high-speed and power-efficient systems have resulted into the emergence of the approximate computing. Existing approximate circuits as well as stochastic techniques have shown promising advances in improving various figures of merit. However, a through fair comparison of arithmetic units still remains an issue which has not been studied. This paper reviews the prerequisites for a fair comparison of approximate arithmetic units. As one of the key components of arithmetic circuits, adders are the focus of this paper. For the first time in this paper, approximate and exact adders are studied together in the stochastic regime. Simulation results show that both the equal segmentation adder (ESA) and the error tolerant adder type II (ETAII) outperform exact adders working stochastically, if and only if the right configuration and sub-adder architectures are chosen. Otherwise, there is no reason to use the aforementioned architectures. In all, considering the cost-error trade-off, Lower-part OR adder (LOA) has the best behavior in the stochastic regime.
UR - http://www.scopus.com/inward/record.url?scp=85043462257&partnerID=8YFLogxK
U2 - 10.1109/patmos.2017.8106990
DO - 10.1109/patmos.2017.8106990
M3 - Conference contribution
AN - SCOPUS:85043462257
SP - 1
EP - 6
BT - 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017
Y2 - 25 September 2017 through 27 September 2017
ER -