Details
| Original language | English |
|---|---|
| Title of host publication | 2016 Pan Pacific Microelectronics Symposium, Pan Pacific 2016 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (electronic) | 9780988887398 |
| Publication status | Published - 7 Mar 2016 |
| Event | Pan Pacific Microelectronics Symposium, Pan Pacific 2016 - Big Island, United States Duration: 25 Jan 2016 → 28 Jan 2016 |
Abstract
Mission profiles for semiconductor applications are getting more and more challenging regarding electrical and thermo-mechanical robustness of metallization stacks. Effects, especially in thick metals, were investigated over the last years to find solutions for an improvement regarding both potential stressors. Some elements of a metallization were designed, investigated and simulated [1, 2, 3, 4 5]. But for an implementation in products it is necessary to develop a complete metallization stack. Therefore a support for layout tools is indispensable. This paper will explain the principles of a highly robust AlCu-metallization stack, the physics and failure mechanisms which are considered for some elements of such a metal stack and the design solution.
Keywords
- design, high temperature AlCu-metallization, interconnect reliability, layout implementation, lifetime, robustness, stress
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
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2016 Pan Pacific Microelectronics Symposium, Pan Pacific 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7428423.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A design for highly robust ALCU-W-PLUG-metallization stack
AU - Hein, V.
AU - Ackermann, M.
AU - Erstling, M.
AU - Liew, J.
AU - Weide-Zaage, K.
N1 - Publisher Copyright: © 2016 SMTA. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2016/3/7
Y1 - 2016/3/7
N2 - Mission profiles for semiconductor applications are getting more and more challenging regarding electrical and thermo-mechanical robustness of metallization stacks. Effects, especially in thick metals, were investigated over the last years to find solutions for an improvement regarding both potential stressors. Some elements of a metallization were designed, investigated and simulated [1, 2, 3, 4 5]. But for an implementation in products it is necessary to develop a complete metallization stack. Therefore a support for layout tools is indispensable. This paper will explain the principles of a highly robust AlCu-metallization stack, the physics and failure mechanisms which are considered for some elements of such a metal stack and the design solution.
AB - Mission profiles for semiconductor applications are getting more and more challenging regarding electrical and thermo-mechanical robustness of metallization stacks. Effects, especially in thick metals, were investigated over the last years to find solutions for an improvement regarding both potential stressors. Some elements of a metallization were designed, investigated and simulated [1, 2, 3, 4 5]. But for an implementation in products it is necessary to develop a complete metallization stack. Therefore a support for layout tools is indispensable. This paper will explain the principles of a highly robust AlCu-metallization stack, the physics and failure mechanisms which are considered for some elements of such a metal stack and the design solution.
KW - design
KW - high temperature AlCu-metallization
KW - interconnect reliability
KW - layout implementation
KW - lifetime
KW - robustness
KW - stress
UR - http://www.scopus.com/inward/record.url?scp=84964967649&partnerID=8YFLogxK
U2 - 10.1109/panpacific.2016.7428423
DO - 10.1109/panpacific.2016.7428423
M3 - Conference contribution
AN - SCOPUS:84964967649
BT - 2016 Pan Pacific Microelectronics Symposium, Pan Pacific 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Pan Pacific Microelectronics Symposium, Pan Pacific 2016
Y2 - 25 January 2016 through 28 January 2016
ER -