Details
| Original language | English |
|---|---|
| Pages (from-to) | 37-47 |
| Number of pages | 11 |
| Journal | Journal of VLSI Signal Processing |
| Volume | 5 |
| Issue number | 1 |
| Publication status | Published - 1 Jan 1993 |
Abstract
An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real time image processing applications has been full-custom designed and fabricated using standard CMOS technology. The bit-serial systolic array incorporates new architectural concepts and circuit techniques fitting a defect tolerant design approach. Therefore high performance and high yield enhancement is achieved. The defect tolerance techniques are based on software controlled defect localization and reconfiguration with programmable switches by a host-processor or a VLSI-tester. The chips functionality differs to available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip line delays and implemented special processing of frames borders. High performance implementations of signal processing algorithms require large chip die sizes. The presented defect tolerance techniques and architectural concepts make systolic large area implementations of signal processing algorithms feasible.
ASJC Scopus subject areas
- Computer Science(all)
- Signal Processing
- Computer Science(all)
- Information Systems
- Engineering(all)
- Electrical and Electronic Engineering
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In: Journal of VLSI Signal Processing, Vol. 5, No. 1, 01.01.1993, p. 37-47.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - A defect-tolerant systolic array implementation for real time image processing
AU - Hecht, V.
AU - Rönner, K.
AU - Pirsch, P.
PY - 1993/1/1
Y1 - 1993/1/1
N2 - An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real time image processing applications has been full-custom designed and fabricated using standard CMOS technology. The bit-serial systolic array incorporates new architectural concepts and circuit techniques fitting a defect tolerant design approach. Therefore high performance and high yield enhancement is achieved. The defect tolerance techniques are based on software controlled defect localization and reconfiguration with programmable switches by a host-processor or a VLSI-tester. The chips functionality differs to available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip line delays and implemented special processing of frames borders. High performance implementations of signal processing algorithms require large chip die sizes. The presented defect tolerance techniques and architectural concepts make systolic large area implementations of signal processing algorithms feasible.
AB - An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real time image processing applications has been full-custom designed and fabricated using standard CMOS technology. The bit-serial systolic array incorporates new architectural concepts and circuit techniques fitting a defect tolerant design approach. Therefore high performance and high yield enhancement is achieved. The defect tolerance techniques are based on software controlled defect localization and reconfiguration with programmable switches by a host-processor or a VLSI-tester. The chips functionality differs to available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip line delays and implemented special processing of frames borders. High performance implementations of signal processing algorithms require large chip die sizes. The presented defect tolerance techniques and architectural concepts make systolic large area implementations of signal processing algorithms feasible.
UR - http://www.scopus.com/inward/record.url?scp=0027311507&partnerID=8YFLogxK
U2 - 10.1007/BF01880270
DO - 10.1007/BF01880270
M3 - Article
AN - SCOPUS:0027311507
VL - 5
SP - 37
EP - 47
JO - Journal of VLSI Signal Processing
JF - Journal of VLSI Signal Processing
SN - 0922-5773
IS - 1
ER -