Details
| Original language | English |
|---|---|
| Title of host publication | ISCAS 2024 - IEEE International Symposium on Circuits and Systems |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (electronic) | 9798350330991 |
| Publication status | Published - 2024 |
| Event | 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - , Singapore Duration: 19 May 2024 → 22 May 2024 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| ISSN (Print) | 0271-4310 |
Abstract
This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.
Keywords
- analog-to-digital converter, hardware-sharing, incremental delta-sigma modulator, linearization, time-interleaved
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2024. (Proceedings - IEEE International Symposium on Circuits and Systems).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs
AU - Flemming, Jesko
AU - Wicht, Bernhard
AU - Witte, Pascal
PY - 2024
Y1 - 2024
N2 - This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.
AB - This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.
KW - analog-to-digital converter
KW - hardware-sharing
KW - incremental delta-sigma modulator
KW - linearization
KW - time-interleaved
UR - http://www.scopus.com/inward/record.url?scp=85198505317&partnerID=8YFLogxK
U2 - 10.1109/ISCAS58744.2024.10557987
DO - 10.1109/ISCAS58744.2024.10557987
M3 - Conference contribution
AN - SCOPUS:85198505317
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - ISCAS 2024 - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024
Y2 - 19 May 2024 through 22 May 2024
ER -