Details
| Original language | English |
|---|---|
| Title of host publication | 2004 IEEE International Symposium on Consumer Electronics - Proceedings |
| Pages | 142-145 |
| Number of pages | 4 |
| Publication status | Published - 2004 |
| Event | 2004 IEEE International Symposium on Consumer Electronics - Reading, United Kingdom (UK) Duration: 1 Sept 2004 → 3 Sept 2004 |
Publication series
| Name | 2004 IEEE International Symposium on Consumer Electronics - Proceedings |
|---|
Abstract
This paper describes a coprocessor for intelligent image and video processing in real-time, which was developed within the European IST-2001-34410 CAMELLIA project. The coprocessor accelerates low- and mid-level smart imaging functions and aims at System-on-Chip (SoC) solutions for applications in the automotive and mobile communication domain. Within the CAMELLIA project the coprocessor is employed to enhance an existing video compression core with smart imaging functionality. The coprocessor was implemented in a 90 nm CMOS technology to run at 150 MHz.
Keywords
- Image processing, Smart imaging, VLSI coprocessor architecture
ASJC Scopus subject areas
- Engineering(all)
- General Engineering
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2004 IEEE International Symposium on Consumer Electronics - Proceedings. 2004. p. 142-145 (2004 IEEE International Symposium on Consumer Electronics - Proceedings).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A coprocessor for intelligent image and video processing in the automotive and mobile communication domain
AU - Jachalsky, Jörn
AU - Wahle, Martin
AU - Pirsch, Peter
AU - Gehrke, Winfried
AU - Hinz, Thomas
PY - 2004
Y1 - 2004
N2 - This paper describes a coprocessor for intelligent image and video processing in real-time, which was developed within the European IST-2001-34410 CAMELLIA project. The coprocessor accelerates low- and mid-level smart imaging functions and aims at System-on-Chip (SoC) solutions for applications in the automotive and mobile communication domain. Within the CAMELLIA project the coprocessor is employed to enhance an existing video compression core with smart imaging functionality. The coprocessor was implemented in a 90 nm CMOS technology to run at 150 MHz.
AB - This paper describes a coprocessor for intelligent image and video processing in real-time, which was developed within the European IST-2001-34410 CAMELLIA project. The coprocessor accelerates low- and mid-level smart imaging functions and aims at System-on-Chip (SoC) solutions for applications in the automotive and mobile communication domain. Within the CAMELLIA project the coprocessor is employed to enhance an existing video compression core with smart imaging functionality. The coprocessor was implemented in a 90 nm CMOS technology to run at 150 MHz.
KW - Image processing
KW - Smart imaging
KW - VLSI coprocessor architecture
UR - http://www.scopus.com/inward/record.url?scp=10444243240&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:10444243240
SN - 0780385276
T3 - 2004 IEEE International Symposium on Consumer Electronics - Proceedings
SP - 142
EP - 145
BT - 2004 IEEE International Symposium on Consumer Electronics - Proceedings
T2 - 2004 IEEE International Symposium on Consumer Electronics
Y2 - 1 September 2004 through 3 September 2004
ER -