Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the International Symposium on Power Semiconductor Devices and ICs |
| Subtitle of host publication | ISPSD 2017 |
| Pages | 171-174 |
| Number of pages | 4 |
| ISBN (electronic) | 978-4-88686-096-5 |
| Publication status | Published - 2017 |
| Event | 29th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2017 - Sapporo, Japan Duration: 28 May 2017 → 1 Jun 2017 |
Publication series
| Name | Proceedings of the International Symposium on Power Semiconductor Devices and ICs |
|---|---|
| ISSN (Print) | 1063-6854 |
Abstract
This paper proposes a point-to-point modeling scheme for Spice-based circuit simulation of parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. An automated layout extraction identifies the perturbators and the sensitive devices and determines the parameters for the models. The equations of the models are derived from calibrated TCAD simulations based on measurements of a dedicated test chip. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip.
Keywords
- Circuit modeling, Minority carrier injection, Parasitic substrate coupling, Smart Power IC
ASJC Scopus subject areas
- Engineering(all)
- General Engineering
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Proceedings of the International Symposium on Power Semiconductor Devices and ICs: ISPSD 2017. 2017. p. 171-174 (Proceedings of the International Symposium on Power Semiconductor Devices and ICs).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A circuit simulation flow for substrate minority carrier injection in smart power ICs
AU - Kollmitzer, Michael
AU - Olbrich, Markus
AU - Barke, Erich
N1 - Funding Information: VIII. ACKNOWLEDGMENTS Part of this work was performed under eRAMP project (621270/2013) funded by grants from ENIAC JU, EU. The project eRamp is co-funded by grants from Germany, Austria, Slovakia and the ENIAC Joint Undertaking. It is coordinated by Infineon Technologies Dresden GmbH.
PY - 2017
Y1 - 2017
N2 - This paper proposes a point-to-point modeling scheme for Spice-based circuit simulation of parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. An automated layout extraction identifies the perturbators and the sensitive devices and determines the parameters for the models. The equations of the models are derived from calibrated TCAD simulations based on measurements of a dedicated test chip. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip.
AB - This paper proposes a point-to-point modeling scheme for Spice-based circuit simulation of parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. An automated layout extraction identifies the perturbators and the sensitive devices and determines the parameters for the models. The equations of the models are derived from calibrated TCAD simulations based on measurements of a dedicated test chip. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip.
KW - Circuit modeling
KW - Minority carrier injection
KW - Parasitic substrate coupling
KW - Smart Power IC
UR - http://www.scopus.com/inward/record.url?scp=85028516364&partnerID=8YFLogxK
U2 - 10.23919/ispsd.2017.7988946
DO - 10.23919/ispsd.2017.7988946
M3 - Conference contribution
AN - SCOPUS:85028516364
SN - 978-4-88686-094-1
T3 - Proceedings of the International Symposium on Power Semiconductor Devices and ICs
SP - 171
EP - 174
BT - Proceedings of the International Symposium on Power Semiconductor Devices and ICs
T2 - 29th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2017
Y2 - 28 May 2017 through 1 June 2017
ER -