Details
| Original language | English |
|---|---|
| Pages (from-to) | 223-233 |
| Number of pages | 11 |
| Journal | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology |
| Volume | 43 |
| Issue number | 2 |
| Publication status | Published - 1 Jun 2006 |
| Externally published | Yes |
Abstract
This paper presents an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze on-chip communication. In order to demonstrate the suitability of this approach, the on-chip communication structure of two examples featuring typical system-on-chip (SoC) communication conflicts like competition for common communication resources have been studied. A state-of-the-art heterogeneous digital signal processor (DSP) and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.
Keywords
- Design space exploration, Performance estimation, Performance modeling, Petri nets, SoC communication
ASJC Scopus subject areas
- Computer Science(all)
- Signal Processing
- Computer Science(all)
- Information Systems
- Engineering(all)
- Electrical and Electronic Engineering
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In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 43, No. 2, 01.06.2006, p. 223-233.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication Domain
AU - Blume, H.
AU - Von Sydow, T.
AU - Noll, T. G.
PY - 2006/6/1
Y1 - 2006/6/1
N2 - This paper presents an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze on-chip communication. In order to demonstrate the suitability of this approach, the on-chip communication structure of two examples featuring typical system-on-chip (SoC) communication conflicts like competition for common communication resources have been studied. A state-of-the-art heterogeneous digital signal processor (DSP) and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.
AB - This paper presents an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze on-chip communication. In order to demonstrate the suitability of this approach, the on-chip communication structure of two examples featuring typical system-on-chip (SoC) communication conflicts like competition for common communication resources have been studied. A state-of-the-art heterogeneous digital signal processor (DSP) and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.
KW - Design space exploration
KW - Performance estimation
KW - Performance modeling
KW - Petri nets
KW - SoC communication
UR - http://www.scopus.com/inward/record.url?scp=33744727692&partnerID=8YFLogxK
U2 - 10.1007/s11265-006-7272-4
DO - 10.1007/s11265-006-7272-4
M3 - Article
AN - SCOPUS:33744727692
VL - 43
SP - 223
EP - 233
JO - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
JF - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
SN - 1387-5485
IS - 2
ER -