Details
| Original language | English |
|---|---|
| Title of host publication | ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference |
| Editors | Pietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso |
| Pages | 151-154 |
| Number of pages | 4 |
| ISBN (electronic) | 9781479956944 |
| Publication status | Published - 31 Oct 2014 |
| Externally published | Yes |
| Event | 40th European Solid-State Circuit Conference, ESSCIRC 2014 - Venezia Lido, Italy Duration: 22 Sept 2014 → 26 Sept 2014 |
Publication series
| Name | European Solid-State Circuits Conference |
|---|---|
| ISSN (Print) | 1930-8833 |
Abstract
Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Electrical and Electronic Engineering
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ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. ed. / Pietro Andreani; Andrea Bevilacqua; Gaudenzio Meneghesso. 2014. p. 151-154 6942044 (European Solid-State Circuits Conference).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters
AU - Wittmann, Juergen
AU - Rosahl, Thoralf
AU - Wicht, Bernhard
N1 - Publisher Copyright: © 2014 IEEE.
PY - 2014/10/31
Y1 - 2014/10/31
N2 - Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.
AB - Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.
UR - http://www.scopus.com/inward/record.url?scp=84909965863&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2014.6942044
DO - 10.1109/ESSCIRC.2014.6942044
M3 - Conference contribution
AN - SCOPUS:84909965863
T3 - European Solid-State Circuits Conference
SP - 151
EP - 154
BT - ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
A2 - Andreani, Pietro
A2 - Bevilacqua, Andrea
A2 - Meneghesso, Gaudenzio
T2 - 40th European Solid-State Circuit Conference, ESSCIRC 2014
Y2 - 22 September 2014 through 26 September 2014
ER -