Details
| Original language | English |
|---|---|
| Title of host publication | 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) |
| Pages | 1-4 |
| ISBN (electronic) | 978-1-7281-0655-7 |
| Publication status | Published - Apr 2019 |
| Event | 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - , Taiwan Duration: 22 Apr 2019 → 25 Apr 2019 |
Abstract
The growing application scope of non-volatile memory based microcontrollers leads to increased memory capacity requirements. Scaling issues of established flash technologies impede further increase of memory density. Emerging technologies still suffer from a lack of robustness for automotive application. This paper presents the first embedded multi-level cell flash memory macro for automotive application manufactured in 28 nm technology. It employs a robust time-domain voltage sensing scheme with ramped gate cell biasing to achieve low latency combined with increased fault tolerance. Measurement results show widened time-domain read windows when applying dynamic voltage ramps to the word lines. The 16 Mb memory features 30 ns random access time at temperatures up to 175 °C with 2b/cell operation. Retention bit error rates below 80 ppm are achieved after 1 k programming and erasing cycles.
Keywords
- Embedded flash, Multi-level flash, Time-domain sensing, Voltage sensing
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
- Engineering(all)
- Safety, Risk, Reliability and Quality
- Physics and Astronomy(all)
- Instrumentation
- Computer Science(all)
- Computer Networks and Communications
- Computer Science(all)
- Hardware and Architecture
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2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). 2019. p. 1-4 8741536.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application
AU - Kiesel, Sebastian
AU - Kern, Thomas
AU - Wicht, Bernhard
AU - Graeb, Helmut
N1 - DBLP's bibliographic metadata records provided through http://dblp.org/search/publ/api are distributed under a Creative Commons CC0 1.0 Universal Public Domain Dedication. Although the bibliographic metadata records are provided consistent with CC0 1.0 Dedication, the content described by the metadata records is not. Content may be subject to copyright, rights of privacy, rights of publicity and other restrictions.
PY - 2019/4
Y1 - 2019/4
N2 - The growing application scope of non-volatile memory based microcontrollers leads to increased memory capacity requirements. Scaling issues of established flash technologies impede further increase of memory density. Emerging technologies still suffer from a lack of robustness for automotive application. This paper presents the first embedded multi-level cell flash memory macro for automotive application manufactured in 28 nm technology. It employs a robust time-domain voltage sensing scheme with ramped gate cell biasing to achieve low latency combined with increased fault tolerance. Measurement results show widened time-domain read windows when applying dynamic voltage ramps to the word lines. The 16 Mb memory features 30 ns random access time at temperatures up to 175 °C with 2b/cell operation. Retention bit error rates below 80 ppm are achieved after 1 k programming and erasing cycles.
AB - The growing application scope of non-volatile memory based microcontrollers leads to increased memory capacity requirements. Scaling issues of established flash technologies impede further increase of memory density. Emerging technologies still suffer from a lack of robustness for automotive application. This paper presents the first embedded multi-level cell flash memory macro for automotive application manufactured in 28 nm technology. It employs a robust time-domain voltage sensing scheme with ramped gate cell biasing to achieve low latency combined with increased fault tolerance. Measurement results show widened time-domain read windows when applying dynamic voltage ramps to the word lines. The 16 Mb memory features 30 ns random access time at temperatures up to 175 °C with 2b/cell operation. Retention bit error rates below 80 ppm are achieved after 1 k programming and erasing cycles.
KW - Embedded flash
KW - Multi-level flash
KW - Time-domain sensing
KW - Voltage sensing
UR - http://www.scopus.com/inward/record.url?scp=85068591099&partnerID=8YFLogxK
UR - https://dblp.org/rec/conf/vlsi-dat/KieselKWG19
U2 - 10.1109/vlsi-dat.2019.8741536
DO - 10.1109/vlsi-dat.2019.8741536
M3 - Conference contribution
SN - 978-1-7281-0656-4
SP - 1
EP - 4
BT - 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
T2 - 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
Y2 - 22 April 2019 through 25 April 2019
ER -