The benefits and acceptance of hearing aids can only be guaranteed if the complex technical constraints are met. These constraints include miniaturized designs, very short latencies in audio signal processing and, in particular, an extremely limited power dissipation budget to achieve long battery life.

At the same time, modern and powerful algorithms for digital hearing aids require high computing power. The Smart HeaP project will address this need for powerful and extremely low-loss processor architectures for digital hearing aids. For this purpose, a fully programmable ASIP (Application Specific Instruction Set Processor) architecture will be designed and implemented. This processor architecture will be based on an audio ASIP architecture and will be adapted to the requirements of modern powerful algorithms by means of specific instruction set extensions and specific accelerator design. By using a design environment, the chip will be fully programmable in high-level languages and thus enables further algorithmic developments.

To achieve an extremly low power consumption, a 22nm FDSOI (Fully Depleted Silicon on Insulator) technology will be used. The novel use of this semiconductor technology in hearing aid processors, for example, leads to drastically reduced leakage currents and thus to significantly reduced power dissipation. The final chip is integrated as a mixed-signal ASIC design, which contains the ASIP processor core and other components such as AD/DA converters and communication modules such as Bluetooth low-energy.

The final hearing aid chip is integrated into a demonstrator hearing aid.

At the Department of Architecture and Systems of the Institute of Microelectronic Systems, application-specific instruction set extensibility and the mapping of powerful hearing aid algorithms to the ASIP architecture are being researched.