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Laboratorium für Informationstechnologie (LFI)

Organisational unit: former organisational unit

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Publications

  1. 1996
  2. Published

    Object based data cache with conflict free concurrent access as shared memory for a parallel DSP

    Kneip, J. & Pirsch, P., 1996, p. 25-34. 10 p.

    Research output: Contribution to conference › Paper › Research › peer review

  3. Published

    Parallel implementation of medium level algorithms on a monolithic ASIMD multiprocessor

    Kneip, J., Ohmacht, M., Wittenburg, J. P. & Pirsch, P., 1996, In: Proceedings - IEEE International Symposium on Circuits and Systems. 4, p. 316-319 4 p.

    Research output: Contribution to journal › Conference article › Research › peer review

  4. Published

    System level HW/SW partitioning and optimization tool

    Schwiegershausen, M., Kropp, H. & Pirsch, P., 1996, p. 120-125. 6 p.

    Research output: Contribution to conference › Paper › Research › peer review

  5. 1995
  6. Published

    Model calculations on a bipolar transistor emitter interconnection with different contact shapes

    Weide, K., Ullmann, J. & Hasse, W., 2 Oct 1995, In: Applied surface science. 91, 1-4, p. 234-238 5 p.

    Research output: Contribution to journal › Article › Research › peer review

  7. Published

    The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques

    Schönfeld, M., Franzen, J., Schwiegershausen, M., Pirsch, P., Vehlies, U. & Münzner, A., 1 Oct 1995, In: Journal of VLSI Signal Processing. 11, 1-2, p. 51-74 24 p.

    Research output: Contribution to journal › Article › Research › peer review

  8. Published

    Architecture and C++-programming environment of a highly parallel image signal processor

    Kneip, J., Ohmacht, M., Rönner, K. & Pirsch, P., Oct 1995, In: Microprocessing and Microprogramming. 41, 5-6, p. 391-408 18 p.

    Research output: Contribution to journal › Article › Research › peer review

  9. Published

    VLSI Architectures for Video Compression: A Survey

    Pirsch, P., Gehrke, W. & Demassieux, N., Feb 1995, In: Proceedings of the IEEE. 83, 2, p. 220-246 27 p.

    Research output: Contribution to journal › Article › Research › peer review

  10. Published

    VLSI architectures for video signal processing

    Pirsch, P. & Gehrke, W., Feb 1995, In: IEE Conference Publication. 410, p. 6-10 5 p.

    Research output: Contribution to journal › Conference article › Research › peer review

  11. Published

    LOSSYWIRE - a model implementation for transient and AC analysis of lossy coupled transmission lines in the circuit simulator EldoTM

    Grotelueschen, E., Grabinski, H., Rochel, S. & Winkel, T. M., Jan 1995, In: AEU. Archiv fur Elektronik und Ubertragungstechnik. 49, 1, p. 37-43 7 p.

    Research output: Contribution to journal › Article › Research › peer review

  12. Published

    Algorithm adapted autonomous controlling concept for a parallel single-chip digital signal processor

    Kneip, J., Wittenburg, J. P., Berekovic, M., Ronner, K. & Pirsch, P., 1995, p. 41-50. 10 p.

    Research output: Contribution to conference › Paper › Research › peer review

  13. Published

    Architecture and memory requirements for stand-alone and hierarchical MPEG2 HDTV-decoders with synchronous DRAMs

    Winzker, M., Pirsch, P. & Reimers, J., 1995, In: Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 609-612 4 p.

    Research output: Contribution to journal › Conference article › Research › peer review

  14. Published

    Formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes

    Schwiegershausen, M. & Pirsch, P., 1995, p. 8-13. 6 p.

    Research output: Contribution to conference › Paper › Research › peer review

  15. Published

    Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor

    Pirsch, P., Kneip, J. & Roenner, K., 1995, In: Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 562-565 4 p.

    Research output: Contribution to journal › Conference article › Research › peer review

  16. Published

    System level design methodology for the optimization of heterogeneous multiprocessors

    Schwiegershausen, M. & Pirsch, P., 1995, In: Proceedings of the International Symposium on System Synthesis. p. 162-167 6 p.

    Research output: Contribution to journal › Conference article › Research › peer review

  17. Published

    Very large scale integration (VLSI) architectures for video signal processing

    Pirsch, P. & Gehrke, W., 1995, Proceedings of SPIE : The International Society for Optical Engineering. 2/- ed. p. 758-777 20 p. (SPIE - The International Society for Optical Engineering; vol. 2501 , no. 2/-).

    Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

  18. Published

    VLSI architectures for video compression

    Pirsch, P. & Gehrke, W., 1995, p. 49-54. 6 p.

    Research output: Contribution to conference › Paper › Research › peer review

  19. 1994
  20. Published

    A hierarchical multiprocessor architecture based on heterogeneous processors for video coding applications

    Gehrke, W., Hoffer, R. & Pirsch, P., 1994, In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP). 2, p. II413-II416 389633.

    Research output: Contribution to journal › Conference article › Research › peer review

  21. Published

    Data path array with shared memory as core of a high performance DSP

    Kneip, J., Roenner, K. & Pirsch, P., 1994, In: Proceedings of the International Conference on Application Specific Array Processors. p. 271-282 12 p.

    Research output: Contribution to journal › Conference article › Research › peer review

  22. Published

    Single board image processing unit for vehicle guidance

    Schonfeld, J. & Pirsch, P., 1994, IFIP Transactions A: Computer Science and Technology. A-42 ed. p. 151-160 10 p.

    Research output: Chapter in book/report/conference proceeding › Contribution to book/anthology › Research › peer review

  23. Published

    Single-chip highly parallel architecture for image processing applications

    Kneip, J., Roenner, K. & Pirsch, P., 1994, Proceedings of SPIE : The International Society for Optical Engineering. p 3 ed. p. 1753-1764 12 p. (Proceedings of SPIE - The International Society for Optical Engineering; vol. 2308, no. p 3).

    Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

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