VLSI architectures for hierarchical block matching algorithms

Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review

Autoren

  • T. Komarek
  • P. Pirsch

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Details

OriginalspracheEnglisch
Seiten (von - bis)45-48
Seitenumfang4
FachzeitschriftProceedings - IEEE International Symposium on Circuits and Systems
Jahrgang1
PublikationsstatusVeröffentlicht - 1990
Veranstaltung1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
Dauer: 1 Mai 1990 → 3 Mai 1990

Abstract

An application-specific multiprocessor system is investigated for real-time implementation of the hierarchical block matching algorithm. The proposed architecture is based on parallel processing units and local memories which are globally preloaded via a common bus. The performance is estimated for the data transfer and the parallel computation time schedule.

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VLSI architectures for hierarchical block matching algorithms. / Komarek, T.; Pirsch, P.
in: Proceedings - IEEE International Symposium on Circuits and Systems, Jahrgang 1, 1990, S. 45-48.

Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review

Komarek, T & Pirsch, P 1990, 'VLSI architectures for hierarchical block matching algorithms', Proceedings - IEEE International Symposium on Circuits and Systems, Jg. 1, S. 45-48.
Komarek, T., & Pirsch, P. (1990). VLSI architectures for hierarchical block matching algorithms. Proceedings - IEEE International Symposium on Circuits and Systems, 1, 45-48.
Komarek T, Pirsch P. VLSI architectures for hierarchical block matching algorithms. Proceedings - IEEE International Symposium on Circuits and Systems. 1990;1:45-48.
Komarek, T. ; Pirsch, P. / VLSI architectures for hierarchical block matching algorithms. in: Proceedings - IEEE International Symposium on Circuits and Systems. 1990 ; Jahrgang 1. S. 45-48.
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