Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 2457-2460 |
| Seitenumfang | 4 |
| Fachzeitschrift | Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) |
| Jahrgang | 4 |
| Publikationsstatus | Veröffentlicht - 1989 |
| Veranstaltung | 1989 International Conference on Acoustics, Speech, and Signal Processing - Glasgow, Scotland Dauer: 23 Mai 1989 → 26 Mai 1989 |
Abstract
Architectures for the realization of block matching algorithms are discussed, with emphasis on highly concurrent systolic array processors. A mapping methodology for systolic arrays known from the literature is applied to block matching algorithms. Examples of two-dimensional and one-dimensional systolic arrays are presented. The required transistor count and the maximum frame rate for real-time processing of video telephone and TV signals using currently available CMOS technology are estimated.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Software
- Informatik (insg.)
- Signalverarbeitung
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Jahrgang 4, 1989, S. 2457-2460.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - VLSI architectures for block matching algorithms
AU - Komarek, T.
AU - Pirsch, P.
PY - 1989
Y1 - 1989
N2 - Architectures for the realization of block matching algorithms are discussed, with emphasis on highly concurrent systolic array processors. A mapping methodology for systolic arrays known from the literature is applied to block matching algorithms. Examples of two-dimensional and one-dimensional systolic arrays are presented. The required transistor count and the maximum frame rate for real-time processing of video telephone and TV signals using currently available CMOS technology are estimated.
AB - Architectures for the realization of block matching algorithms are discussed, with emphasis on highly concurrent systolic array processors. A mapping methodology for systolic arrays known from the literature is applied to block matching algorithms. Examples of two-dimensional and one-dimensional systolic arrays are presented. The required transistor count and the maximum frame rate for real-time processing of video telephone and TV signals using currently available CMOS technology are estimated.
UR - http://www.scopus.com/inward/record.url?scp=0024879273&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0024879273
VL - 4
SP - 2457
EP - 2460
JO - Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)
JF - Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)
SN - 0736-7791
T2 - 1989 International Conference on Acoustics, Speech, and Signal Processing
Y2 - 23 May 1989 through 26 May 1989
ER -