Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 2-12 |
| Seitenumfang | 11 |
| Fachzeitschrift | Proceedings of SPIE - The International Society for Optical Engineering |
| Jahrgang | 1301 |
| Publikationsstatus | Veröffentlicht - 1990 |
| Veranstaltung | Digital Image Processing and Visual Communications Technologies in the Earth and Atmospheric Sciences - Orlando, FL, USA Dauer: 18 Apr. 1990 → 19 Apr. 1990 |
Abstract
Coding schemes for data rate reduction of digital video signals are being devised for various application areas. Such applications call for video signal processors suited for real-time operation and realization with small size. Small size can be achieved using advanced VLSI technology. Real-time processing of video signals requires several 100 Mega operations per second (MOPS) and correspondingly high data rates for operand transport. These requirements can be met by multiprocessors employing parallelization and pipelining in an adapted architecture. In order to support distinct applications, the multiprocessors have to be programmable. The requirements of video coding schemes have been extracted and mapped into a multiprocessor architecture for programmable real-time video processing. In this contribution, the extracted requirements, the adapted architecture of a multiprocessor, and the multiprocessor modules are presented. The realization of several modules of the multiprocessor using CMOS technology is also reported.
ASJC Scopus Sachgebiete
- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
- Informatik (insg.)
- Angewandte Informatik
- Mathematik (insg.)
- Angewandte Mathematik
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Proceedings of SPIE - The International Society for Optical Engineering, Jahrgang 1301, 1990, S. 2-12.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - VLSI architecture of a programmable real-time video signal processor
AU - Pirsch, Peter
AU - Wehberg, Thomas
PY - 1990
Y1 - 1990
N2 - Coding schemes for data rate reduction of digital video signals are being devised for various application areas. Such applications call for video signal processors suited for real-time operation and realization with small size. Small size can be achieved using advanced VLSI technology. Real-time processing of video signals requires several 100 Mega operations per second (MOPS) and correspondingly high data rates for operand transport. These requirements can be met by multiprocessors employing parallelization and pipelining in an adapted architecture. In order to support distinct applications, the multiprocessors have to be programmable. The requirements of video coding schemes have been extracted and mapped into a multiprocessor architecture for programmable real-time video processing. In this contribution, the extracted requirements, the adapted architecture of a multiprocessor, and the multiprocessor modules are presented. The realization of several modules of the multiprocessor using CMOS technology is also reported.
AB - Coding schemes for data rate reduction of digital video signals are being devised for various application areas. Such applications call for video signal processors suited for real-time operation and realization with small size. Small size can be achieved using advanced VLSI technology. Real-time processing of video signals requires several 100 Mega operations per second (MOPS) and correspondingly high data rates for operand transport. These requirements can be met by multiprocessors employing parallelization and pipelining in an adapted architecture. In order to support distinct applications, the multiprocessors have to be programmable. The requirements of video coding schemes have been extracted and mapped into a multiprocessor architecture for programmable real-time video processing. In this contribution, the extracted requirements, the adapted architecture of a multiprocessor, and the multiprocessor modules are presented. The realization of several modules of the multiprocessor using CMOS technology is also reported.
UR - http://www.scopus.com/inward/record.url?scp=0025555722&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0025555722
VL - 1301
SP - 2
EP - 12
JO - Proceedings of SPIE - The International Society for Optical Engineering
JF - Proceedings of SPIE - The International Society for Optical Engineering
SN - 0277-786X
T2 - Digital Image Processing and Visual Communications Technologies in the Earth and Atmospheric Sciences
Y2 - 18 April 1990 through 19 April 1990
ER -