TY - JOUR

T1 - Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

AU - Fatahilah, Muhammad Fahlesa

AU - Yu, Feng

AU - Strempel, Klaas

AU - Römer, Friedhard

AU - Maradan, Dario

AU - Meneghini, Matteo

AU - Bakin, Andrey

AU - Hohls, Frank

AU - Schumacher, Hans Werner

AU - Witzigmann, Bernd

AU - Waag, Andreas

AU - Wasisto, Hutomo Suryo

N1 - Funding information: The authors would like to thank A. Schmidt, J. Breitfelder, M. Rühmann, and K.-H. Lachmund for their valuable technical assistances. Authors are also grateful for the planar GaN wafers provided by the members of epitaxy competence center (ec2) of TU Braunschweig (I. Manglano Clavero and C. Margenfeld). This work has been performed within the projects of ‘LENA-OptoSense’ funded by the Lower Saxony Ministry for Science and Culture (MWK) and ‘3D Concepts for Gallium-Nitride Electronics (3D GaN)’ funded by the German Research Foundation (DFG). Support by Ministry of Research, Technology, and Higher Education of the Republic of Indonesia (RISTEKDIKTI) and Indonesian-German Center for Nano and Quantum Technologies (IG-Nano) is also acknowledged. The research activity at University of Padova was partly funded by project “Novel vertical GaN-devices for next generation power conversion”, NoveGaN (University of Padova), through the STARS CoG Grants call.

PY - 2019/12/1

Y1 - 2019/12/1

N2 - This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (Vth) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep Vth shift (ΔVth) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.

AB - This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (Vth) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep Vth shift (ΔVth) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.

UR - http://www.scopus.com/inward/record.url?scp=85069434887&partnerID=8YFLogxK

U2 - 10.1038/s41598-019-46186-9

DO - 10.1038/s41598-019-46186-9

M3 - Article

C2 - 31311946

AN - SCOPUS:85069434887

VL - 9

JO - Scientific reports

JF - Scientific reports

SN - 2045-2322

IS - 1

M1 - 10301

ER -