Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 1625-1630 |
| Seitenumfang | 6 |
| Fachzeitschrift | Microelectronics reliability |
| Jahrgang | 41 |
| Ausgabenummer | 9-10 |
| Publikationsstatus | Veröffentlicht - Sept. 2001 |
Abstract
The understanding of metal migration mechanisms remains today a big interest. Metallization structures are getting more and more smaller whereas the reliability of integrated circuits needs to be improved. The increasing capacities of numerical analysis and simulation tools like the Finite Element Method (FEM) allow the prediction of failure location degradation caused by this phenomena. In this paper, an algorithm for 3-D simulation of void formation in metallizations is presented, taking into account the electromigration, as well as the thermomigration and the stressmigration contributions. Two typical structures like a meander- and a pad structure are investigated. The void evolution inside the metallization structure, as well as the change of the electrical resistivity of the interconnect are simulated. A new method for the time-dependent calculation of the phenomena is also proposed, and an evaluation of the Time-To-Failure (TTF) for the investigated structures is presented. The results obtained by simulation are found in good agreement with SEM observations.
ASJC Scopus Sachgebiete
- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
- Physik und Astronomie (insg.)
- Atom- und Molekularphysik sowie Optik
- Ingenieurwesen (insg.)
- Sicherheit, Risiko, Zuverlässigkeit und Qualität
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
- Werkstoffwissenschaften (insg.)
- Oberflächen, Beschichtungen und Folien
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
Zitieren
- Standard
- Harvard
- Apa
- Vancouver
- BibTex
- RIS
in: Microelectronics reliability, Jahrgang 41, Nr. 9-10, 09.2001, S. 1625-1630.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Three-dimensional voids simulation in chip metallization structures
T2 - A contribution to reliability evaluation
AU - Dalleau, D.
AU - Weide-Zaage, K.
N1 - Copyright: Copyright 2007 Elsevier B.V., All rights reserved.
PY - 2001/9
Y1 - 2001/9
N2 - The understanding of metal migration mechanisms remains today a big interest. Metallization structures are getting more and more smaller whereas the reliability of integrated circuits needs to be improved. The increasing capacities of numerical analysis and simulation tools like the Finite Element Method (FEM) allow the prediction of failure location degradation caused by this phenomena. In this paper, an algorithm for 3-D simulation of void formation in metallizations is presented, taking into account the electromigration, as well as the thermomigration and the stressmigration contributions. Two typical structures like a meander- and a pad structure are investigated. The void evolution inside the metallization structure, as well as the change of the electrical resistivity of the interconnect are simulated. A new method for the time-dependent calculation of the phenomena is also proposed, and an evaluation of the Time-To-Failure (TTF) for the investigated structures is presented. The results obtained by simulation are found in good agreement with SEM observations.
AB - The understanding of metal migration mechanisms remains today a big interest. Metallization structures are getting more and more smaller whereas the reliability of integrated circuits needs to be improved. The increasing capacities of numerical analysis and simulation tools like the Finite Element Method (FEM) allow the prediction of failure location degradation caused by this phenomena. In this paper, an algorithm for 3-D simulation of void formation in metallizations is presented, taking into account the electromigration, as well as the thermomigration and the stressmigration contributions. Two typical structures like a meander- and a pad structure are investigated. The void evolution inside the metallization structure, as well as the change of the electrical resistivity of the interconnect are simulated. A new method for the time-dependent calculation of the phenomena is also proposed, and an evaluation of the Time-To-Failure (TTF) for the investigated structures is presented. The results obtained by simulation are found in good agreement with SEM observations.
UR - http://www.scopus.com/inward/record.url?scp=0035456975&partnerID=8YFLogxK
U2 - 10.1016/S0026-2714(01)00151-2
DO - 10.1016/S0026-2714(01)00151-2
M3 - Article
AN - SCOPUS:0035456975
VL - 41
SP - 1625
EP - 1630
JO - Microelectronics reliability
JF - Microelectronics reliability
SN - 0026-2714
IS - 9-10
ER -