Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 51-74 |
| Seitenumfang | 24 |
| Fachzeitschrift | Journal of VLSI Signal Processing |
| Jahrgang | 11 |
| Ausgabenummer | 1-2 |
| Publikationsstatus | Veröffentlicht - 1 Okt. 1995 |
Abstract
The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Signalverarbeitung
- Informatik (insg.)
- Information systems
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Journal of VLSI Signal Processing, Jahrgang 11, Nr. 1-2, 01.10.1995, S. 51-74.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques
AU - Schönfeld, Mirjam
AU - Franzen, Jens
AU - Schwiegershausen, Markus
AU - Pirsch, Peter
AU - Vehlies, Uwe
AU - Münzner, Andreas
PY - 1995/10/1
Y1 - 1995/10/1
N2 - The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability.
AB - The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability.
UR - http://www.scopus.com/inward/record.url?scp=0029389408&partnerID=8YFLogxK
U2 - 10.1007/BF02106823
DO - 10.1007/BF02106823
M3 - Article
AN - SCOPUS:0029389408
VL - 11
SP - 51
EP - 74
JO - Journal of VLSI Signal Processing
JF - Journal of VLSI Signal Processing
SN - 0922-5773
IS - 1-2
ER -