Temperature-dependent contact resistance of carrier selective Poly-Si on oxide junctions

Publikation: Beitrag in FachzeitschriftArtikelForschungPeer-Review

Autoren

  • Nils Folchert
  • Michael Rienäcker
  • A. A. Yeo
  • Byungsul Min
  • Robby Peibst
  • Rolf Brendel

Externe Organisationen

  • Institut für Solarenergieforschung GmbH (ISFH)
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Details

OriginalspracheEnglisch
Seiten (von - bis)425-430
Seitenumfang6
FachzeitschriftSolar Energy Materials and Solar Cells
Jahrgang185
Frühes Online-Datum7 Juni 2018
PublikationsstatusVeröffentlicht - Okt. 2018

Abstract

Carrier selective junctions using a poly-silicon/ silicon oxide stack on crystalline silicon feature low recombination currents J0 whilst allowing for low contact resistivity ρC. We describe the limiting current transport mechanism as a combination of homogeneous tunneling through the interfacial silicon oxide layer and transport through pinholes where the interfacial silicon oxide layer is locally disrupted. We present an experimental method and its theoretical basis to discriminate between homogenous tunneling and local pinhole transport mechanisms on n + /n or p + /p junctions by measuring the temperature-dependent contact resistance. Theory predicts opposing trends for the temperature dependencies of tunneling and pinhole transport. This allows identifying the dominant transport path. For the contact resistance of two differently prepared poly-Si/ silicon oxide/ c-Si junctions we either find clear pinhole-type or clear tunneling-type temperature dependence. Pinhole transport contributes more than 94% to the total current for the sample with a 2.1 nm-thick interfacial silicon oxide that we anneal at a temperature of 1050 °C to achieve highest selectivity. In contrast pinhole transport contributes less than 35 % to the total current for the sample with a 1.7 nm-thick silicon oxide that we annealed at only 700 °C in order to avoid pinholes.

ASJC Scopus Sachgebiete

Ziele für nachhaltige Entwicklung

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Temperature-dependent contact resistance of carrier selective Poly-Si on oxide junctions. / Folchert, Nils; Rienäcker, Michael; Yeo, A. A. et al.
in: Solar Energy Materials and Solar Cells, Jahrgang 185, 10.2018, S. 425-430.

Publikation: Beitrag in FachzeitschriftArtikelForschungPeer-Review

Folchert N, Rienäcker M, Yeo AA, Min B, Peibst R, Brendel R. Temperature-dependent contact resistance of carrier selective Poly-Si on oxide junctions. Solar Energy Materials and Solar Cells. 2018 Okt;185:425-430. Epub 2018 Jun 7. doi: 10.1016/j.solmat.2018.05.046
Folchert, Nils ; Rienäcker, Michael ; Yeo, A. A. et al. / Temperature-dependent contact resistance of carrier selective Poly-Si on oxide junctions. in: Solar Energy Materials and Solar Cells. 2018 ; Jahrgang 185. S. 425-430.
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abstract = "Carrier selective junctions using a poly-silicon/ silicon oxide stack on crystalline silicon feature low recombination currents J0 whilst allowing for low contact resistivity ρC. We describe the limiting current transport mechanism as a combination of homogeneous tunneling through the interfacial silicon oxide layer and transport through pinholes where the interfacial silicon oxide layer is locally disrupted. We present an experimental method and its theoretical basis to discriminate between homogenous tunneling and local pinhole transport mechanisms on n + /n or p + /p junctions by measuring the temperature-dependent contact resistance. Theory predicts opposing trends for the temperature dependencies of tunneling and pinhole transport. This allows identifying the dominant transport path. For the contact resistance of two differently prepared poly-Si/ silicon oxide/ c-Si junctions we either find clear pinhole-type or clear tunneling-type temperature dependence. Pinhole transport contributes more than 94% to the total current for the sample with a 2.1 nm-thick interfacial silicon oxide that we anneal at a temperature of 1050 °C to achieve highest selectivity. In contrast pinhole transport contributes less than 35 % to the total current for the sample with a 1.7 nm-thick silicon oxide that we annealed at only 700 °C in order to avoid pinholes.",
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note = "Funding Information: We thank Guido Glowatzki, Heike Kohlenberger and Sabine Schmidt for their help with sample processing and Manuel Stratmann for the analysis of pinhole densities. We gratefully thank Tobias Wietler (ISFH) and Prof. Uwe Rau (FZ J{\"u}lich) for helpful discussions and hints. This work was supported by the Ministry for Science and Culture of lower Saxony in the framework of the project vOx and has also received funding from the European Union 's Horizon 2020 research and innovation program under grant agreement No 727529 (DISC). Publisher Copyright: {\textcopyright} 2018 Elsevier B.V. Copyright: Copyright 2018 Elsevier B.V., All rights reserved.",
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T1 - Temperature-dependent contact resistance of carrier selective Poly-Si on oxide junctions

AU - Folchert, Nils

AU - Rienäcker, Michael

AU - Yeo, A. A.

AU - Min, Byungsul

AU - Peibst, Robby

AU - Brendel, Rolf

N1 - Funding Information: We thank Guido Glowatzki, Heike Kohlenberger and Sabine Schmidt for their help with sample processing and Manuel Stratmann for the analysis of pinhole densities. We gratefully thank Tobias Wietler (ISFH) and Prof. Uwe Rau (FZ Jülich) for helpful discussions and hints. This work was supported by the Ministry for Science and Culture of lower Saxony in the framework of the project vOx and has also received funding from the European Union 's Horizon 2020 research and innovation program under grant agreement No 727529 (DISC). Publisher Copyright: © 2018 Elsevier B.V. Copyright: Copyright 2018 Elsevier B.V., All rights reserved.

PY - 2018/10

Y1 - 2018/10

N2 - Carrier selective junctions using a poly-silicon/ silicon oxide stack on crystalline silicon feature low recombination currents J0 whilst allowing for low contact resistivity ρC. We describe the limiting current transport mechanism as a combination of homogeneous tunneling through the interfacial silicon oxide layer and transport through pinholes where the interfacial silicon oxide layer is locally disrupted. We present an experimental method and its theoretical basis to discriminate between homogenous tunneling and local pinhole transport mechanisms on n + /n or p + /p junctions by measuring the temperature-dependent contact resistance. Theory predicts opposing trends for the temperature dependencies of tunneling and pinhole transport. This allows identifying the dominant transport path. For the contact resistance of two differently prepared poly-Si/ silicon oxide/ c-Si junctions we either find clear pinhole-type or clear tunneling-type temperature dependence. Pinhole transport contributes more than 94% to the total current for the sample with a 2.1 nm-thick interfacial silicon oxide that we anneal at a temperature of 1050 °C to achieve highest selectivity. In contrast pinhole transport contributes less than 35 % to the total current for the sample with a 1.7 nm-thick silicon oxide that we annealed at only 700 °C in order to avoid pinholes.

AB - Carrier selective junctions using a poly-silicon/ silicon oxide stack on crystalline silicon feature low recombination currents J0 whilst allowing for low contact resistivity ρC. We describe the limiting current transport mechanism as a combination of homogeneous tunneling through the interfacial silicon oxide layer and transport through pinholes where the interfacial silicon oxide layer is locally disrupted. We present an experimental method and its theoretical basis to discriminate between homogenous tunneling and local pinhole transport mechanisms on n + /n or p + /p junctions by measuring the temperature-dependent contact resistance. Theory predicts opposing trends for the temperature dependencies of tunneling and pinhole transport. This allows identifying the dominant transport path. For the contact resistance of two differently prepared poly-Si/ silicon oxide/ c-Si junctions we either find clear pinhole-type or clear tunneling-type temperature dependence. Pinhole transport contributes more than 94% to the total current for the sample with a 2.1 nm-thick interfacial silicon oxide that we anneal at a temperature of 1050 °C to achieve highest selectivity. In contrast pinhole transport contributes less than 35 % to the total current for the sample with a 1.7 nm-thick silicon oxide that we annealed at only 700 °C in order to avoid pinholes.

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KW - Passivating contacts

KW - Pinhole transport

KW - POLO

KW - Poly-Si

KW - Selective contacts

KW - Transfer-length-method

KW - Tunneling

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U2 - 10.1016/j.solmat.2018.05.046

DO - 10.1016/j.solmat.2018.05.046

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JF - Solar Energy Materials and Solar Cells

SN - 0927-0248

ER -