Details
Originalsprache | Englisch |
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Seiten | 120-125 |
Seitenumfang | 6 |
Publikationsstatus | Veröffentlicht - 1996 |
Veranstaltung | 1996 European Design Automation Conference with EURO-VHDL'96 and Exhibition - Geneva, Schweiz Dauer: 16 Sept. 1996 → 20 Sept. 1996 |
Konferenz
Konferenz | 1996 European Design Automation Conference with EURO-VHDL'96 and Exhibition |
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Land/Gebiet | Schweiz |
Ort | Geneva |
Zeitraum | 16 Sept. 1996 → 20 Sept. 1996 |
Abstract
This paper presents a system level HW/SW partitioning methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. Starting from modelling of the signal processing scheme and of the available processor resources, performance and expense measures are estimated for a finite set of processor modules. Based on these measurements, a numerical optimization can be carried out by using mixed integer linear programming as mathematical framework, leading to a heterogeneous system, which is optimal in terms of area expense and throughput rate.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Steuerungs- und Systemtechnik
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1996. 120-125 Beitrag in 1996 European Design Automation Conference with EURO-VHDL'96 and Exhibition, Geneva, Schweiz.
Publikation: Konferenzbeitrag › Paper › Forschung › Peer-Review
}
TY - CONF
T1 - System level HW/SW partitioning and optimization tool
AU - Schwiegershausen, M.
AU - Kropp, H.
AU - Pirsch, P.
PY - 1996
Y1 - 1996
N2 - This paper presents a system level HW/SW partitioning methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. Starting from modelling of the signal processing scheme and of the available processor resources, performance and expense measures are estimated for a finite set of processor modules. Based on these measurements, a numerical optimization can be carried out by using mixed integer linear programming as mathematical framework, leading to a heterogeneous system, which is optimal in terms of area expense and throughput rate.
AB - This paper presents a system level HW/SW partitioning methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. Starting from modelling of the signal processing scheme and of the available processor resources, performance and expense measures are estimated for a finite set of processor modules. Based on these measurements, a numerical optimization can be carried out by using mixed integer linear programming as mathematical framework, leading to a heterogeneous system, which is optimal in terms of area expense and throughput rate.
UR - http://www.scopus.com/inward/record.url?scp=0029728618&partnerID=8YFLogxK
M3 - Paper
AN - SCOPUS:0029728618
SP - 120
EP - 125
T2 - 1996 European Design Automation Conference with EURO-VHDL'96 and Exhibition
Y2 - 16 September 1996 through 20 September 1996
ER -