Details
| Originalsprache | Englisch |
|---|---|
| Aufsatznummer | 9152052 |
| Seiten (von - bis) | 3735-3743 |
| Seitenumfang | 9 |
| Fachzeitschrift | IEEE Journal of Emerging and Selected Topics in Power Electronics |
| Jahrgang | 9 |
| Ausgabenummer | 3 |
| Publikationsstatus | Veröffentlicht - 29 Juli 2020 |
Abstract
The stacking of low-voltage transistors brings several advantages for the design of power management integrated circuits (PMICs). Process nodes and, thereby, the I/O voltage of the core devices shrink down, while the supply voltages of many applications cannot be reduced at the same rate. The stacking of low-voltage devices is often more area- and energy-efficient compared with using one high-voltage transistor. This work proposes an implementation option for the stacking of three low-voltage transistors, which, as a significant advantage, does not require additional supply rails as required in the prior art. It is independent of the input voltage and can, therefore, be widely used in different PMIC designs. The overall article is set up in a survey and tutorial style. It gives an overview of existing solutions and presents best-practice design guidelines for proper implementation of up to four stacked switches. The efficiency benefit of low-voltage transistor stacking over single high-voltage switches is investigated with a model of the transistor stack. Experimental results for loss energy and area consumption of various switch configurations in 130-nm CMOS confirm the presented design aspects. The advantages are also demonstrated by measurement results of a hybrid dc-dc converter with optimized power switch stacking.
ASJC Scopus Sachgebiete
- Energie (insg.)
- Energieanlagenbau und Kraftwerkstechnik
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: IEEE Journal of Emerging and Selected Topics in Power Electronics, Jahrgang 9, Nr. 3, 9152052, 29.07.2020, S. 3735-3743.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Switch Stacking in Power Management ICs
AU - Renz, Peter
AU - Kaufmann, Maik
AU - Lueders, Michael
AU - Wicht, Bernhard
PY - 2020/7/29
Y1 - 2020/7/29
N2 - The stacking of low-voltage transistors brings several advantages for the design of power management integrated circuits (PMICs). Process nodes and, thereby, the I/O voltage of the core devices shrink down, while the supply voltages of many applications cannot be reduced at the same rate. The stacking of low-voltage devices is often more area- and energy-efficient compared with using one high-voltage transistor. This work proposes an implementation option for the stacking of three low-voltage transistors, which, as a significant advantage, does not require additional supply rails as required in the prior art. It is independent of the input voltage and can, therefore, be widely used in different PMIC designs. The overall article is set up in a survey and tutorial style. It gives an overview of existing solutions and presents best-practice design guidelines for proper implementation of up to four stacked switches. The efficiency benefit of low-voltage transistor stacking over single high-voltage switches is investigated with a model of the transistor stack. Experimental results for loss energy and area consumption of various switch configurations in 130-nm CMOS confirm the presented design aspects. The advantages are also demonstrated by measurement results of a hybrid dc-dc converter with optimized power switch stacking.
AB - The stacking of low-voltage transistors brings several advantages for the design of power management integrated circuits (PMICs). Process nodes and, thereby, the I/O voltage of the core devices shrink down, while the supply voltages of many applications cannot be reduced at the same rate. The stacking of low-voltage devices is often more area- and energy-efficient compared with using one high-voltage transistor. This work proposes an implementation option for the stacking of three low-voltage transistors, which, as a significant advantage, does not require additional supply rails as required in the prior art. It is independent of the input voltage and can, therefore, be widely used in different PMIC designs. The overall article is set up in a survey and tutorial style. It gives an overview of existing solutions and presents best-practice design guidelines for proper implementation of up to four stacked switches. The efficiency benefit of low-voltage transistor stacking over single high-voltage switches is investigated with a model of the transistor stack. Experimental results for loss energy and area consumption of various switch configurations in 130-nm CMOS confirm the presented design aspects. The advantages are also demonstrated by measurement results of a hybrid dc-dc converter with optimized power switch stacking.
KW - Adaptive biasing
KW - I/O
KW - cascode bridge
KW - component stacking
KW - dc-dc converter
KW - high-voltage techniques
KW - power stage
KW - transistor stacking
UR - http://www.scopus.com/inward/record.url?scp=85107582556&partnerID=8YFLogxK
U2 - 10.1109/jestpe.2020.3012813
DO - 10.1109/jestpe.2020.3012813
M3 - Article
VL - 9
SP - 3735
EP - 3743
JO - IEEE Journal of Emerging and Selected Topics in Power Electronics
JF - IEEE Journal of Emerging and Selected Topics in Power Electronics
SN - 2168-6777
IS - 3
M1 - 9152052
ER -