Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 319-323 |
| Seitenumfang | 5 |
| Fachzeitschrift | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
| Publikationsstatus | Veröffentlicht - 1998 |
| Veranstaltung | 1998 11th Annual IEEE International ASIC Conference - Rochester, NY, USA Dauer: 13 Sept. 1998 → 16 Sept. 1998 |
Abstract
A video coding subsystem for monolithic integration in a 0.25 μm CMOS technology has been developed. It consists of a programmable video signal processor core, up to 8 Mbit frame memory as embedded DRAM and video interfaces. The functionality of all major components has been verified by implementation on test chips in 0.5 μm CMOS technology. A system realization in 0.25 μm CMOS technology is planned. Investigations show that a die size of less than 89 mm2 for a single chip implementation can be achieved.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 1998, S. 319-323.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Single chip video coding system with embedded DRAM frame memory for stand-alone applications
AU - Herrmann, Klaus
AU - Hilgenstock, Joerg
AU - Pirsch, Peter
PY - 1998
Y1 - 1998
N2 - A video coding subsystem for monolithic integration in a 0.25 μm CMOS technology has been developed. It consists of a programmable video signal processor core, up to 8 Mbit frame memory as embedded DRAM and video interfaces. The functionality of all major components has been verified by implementation on test chips in 0.5 μm CMOS technology. A system realization in 0.25 μm CMOS technology is planned. Investigations show that a die size of less than 89 mm2 for a single chip implementation can be achieved.
AB - A video coding subsystem for monolithic integration in a 0.25 μm CMOS technology has been developed. It consists of a programmable video signal processor core, up to 8 Mbit frame memory as embedded DRAM and video interfaces. The functionality of all major components has been verified by implementation on test chips in 0.5 μm CMOS technology. A system realization in 0.25 μm CMOS technology is planned. Investigations show that a die size of less than 89 mm2 for a single chip implementation can be achieved.
UR - http://www.scopus.com/inward/record.url?scp=0031645401&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0031645401
SP - 319
EP - 323
JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
SN - 1063-0988
T2 - 1998 11th Annual IEEE International ASIC Conference
Y2 - 13 September 1998 through 16 September 1998
ER -