Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 1821-1826 |
| Seitenumfang | 6 |
| Fachzeitschrift | Microelectronics reliability |
| Jahrgang | 43 |
| Ausgabenummer | 9-11 |
| Publikationsstatus | Veröffentlicht - Sept. 2003 |
| Veranstaltung | 14th European Symposium on Reliability of Electron Devices, Fa - Bordeaux, France, Frankreich Dauer: 7 Okt. 2003 → 10 Okt. 2003 |
Abstract
The investigation of degradation phenomena in chip-level metallization structures due to high current densities has been an important challenge since several years. Current densities above IMA/cm2 induce high temperature and temperature gradients as well as high thermo-mechanical stress in the metallization. In addition to this, the formation of voids as well as hillocks appear, due to diffusion induced matter migration, driven by the electrical field, thermal gradients and thermal induced hydrostatic stress gradients. The evaluation of the reliability of metallization structures against metal migration is usually done by accelerated stress tests. A support in failure prediction is possible by finite-element simulations. In this paper, 3-D simulations of void formation in different via structures running under high current densities is presented. The void formation in an aluminum, copper and tungsten plug via structure are compared. The reliability of these different technologies are evaluated by simulation, and the corresponding time-depending results of void formation are presented and analysed. The TTF as well as the increasing electrical resistance of the structures during degradation simulation has been determined.
ASJC Scopus Sachgebiete
- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
- Physik und Astronomie (insg.)
- Atom- und Molekularphysik sowie Optik
- Ingenieurwesen (insg.)
- Sicherheit, Risiko, Zuverlässigkeit und Qualität
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
- Werkstoffwissenschaften (insg.)
- Oberflächen, Beschichtungen und Folien
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Microelectronics reliability, Jahrgang 43, Nr. 9-11, 09.2003, S. 1821-1826.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Simulation of time depending void formation in copper, aluminum and tungsten plugged via structures
AU - Dalleau, David
AU - Weide-Zaage, Kirsten
AU - Danto, Yves
N1 - Copyright: Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2003/9
Y1 - 2003/9
N2 - The investigation of degradation phenomena in chip-level metallization structures due to high current densities has been an important challenge since several years. Current densities above IMA/cm2 induce high temperature and temperature gradients as well as high thermo-mechanical stress in the metallization. In addition to this, the formation of voids as well as hillocks appear, due to diffusion induced matter migration, driven by the electrical field, thermal gradients and thermal induced hydrostatic stress gradients. The evaluation of the reliability of metallization structures against metal migration is usually done by accelerated stress tests. A support in failure prediction is possible by finite-element simulations. In this paper, 3-D simulations of void formation in different via structures running under high current densities is presented. The void formation in an aluminum, copper and tungsten plug via structure are compared. The reliability of these different technologies are evaluated by simulation, and the corresponding time-depending results of void formation are presented and analysed. The TTF as well as the increasing electrical resistance of the structures during degradation simulation has been determined.
AB - The investigation of degradation phenomena in chip-level metallization structures due to high current densities has been an important challenge since several years. Current densities above IMA/cm2 induce high temperature and temperature gradients as well as high thermo-mechanical stress in the metallization. In addition to this, the formation of voids as well as hillocks appear, due to diffusion induced matter migration, driven by the electrical field, thermal gradients and thermal induced hydrostatic stress gradients. The evaluation of the reliability of metallization structures against metal migration is usually done by accelerated stress tests. A support in failure prediction is possible by finite-element simulations. In this paper, 3-D simulations of void formation in different via structures running under high current densities is presented. The void formation in an aluminum, copper and tungsten plug via structure are compared. The reliability of these different technologies are evaluated by simulation, and the corresponding time-depending results of void formation are presented and analysed. The TTF as well as the increasing electrical resistance of the structures during degradation simulation has been determined.
UR - http://www.scopus.com/inward/record.url?scp=0041692468&partnerID=8YFLogxK
U2 - 10.1016/S0026-2714(03)00310-X
DO - 10.1016/S0026-2714(03)00310-X
M3 - Conference article
AN - SCOPUS:0041692468
VL - 43
SP - 1821
EP - 1826
JO - Microelectronics reliability
JF - Microelectronics reliability
SN - 0026-2714
IS - 9-11
T2 - 14th European Symposium on Reliability of Electron Devices, Fa
Y2 - 7 October 2003 through 10 October 2003
ER -