Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings |
| Herausgeber (Verlag) | IEEE Computer Society |
| ISBN (Print) | 9781479925070 |
| Publikationsstatus | Veröffentlicht - 2014 |
| Veranstaltung | 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Santiago, Chile Dauer: 25 Feb. 2014 → 28 Feb. 2014 |
Abstract
The development of 3D-silicon integrated circuits is an increasing demand especially regarding to advanced 3D-packages and high performance applications, with the intend to miniaturize and to reduce costs. Through-silicon-vias (TSV), interconnects and landing pads have a strong mismatch in proportions. Due to high temperature as well as high applied currents, the reliability of the systems and components is affected by thermal and thermal-electrical loads. The induced stress leads to degradation effects like electro- and thermomigration (EM, TM). Mismatch in coefficient of thermal expansion (CTE) are causing mechanical induced stress during the manufacturing process. This can lead to failure mechanisms like delamination and cracking around the TSV or in the ICs.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Hardware und Architektur
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 2014. 6820324.
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Simulation in 3D integration and TSV
AU - Weide-Zaage, K.
AU - Moujbani, A.
AU - Kludt, J.
N1 - Copyright: Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2014
Y1 - 2014
N2 - The development of 3D-silicon integrated circuits is an increasing demand especially regarding to advanced 3D-packages and high performance applications, with the intend to miniaturize and to reduce costs. Through-silicon-vias (TSV), interconnects and landing pads have a strong mismatch in proportions. Due to high temperature as well as high applied currents, the reliability of the systems and components is affected by thermal and thermal-electrical loads. The induced stress leads to degradation effects like electro- and thermomigration (EM, TM). Mismatch in coefficient of thermal expansion (CTE) are causing mechanical induced stress during the manufacturing process. This can lead to failure mechanisms like delamination and cracking around the TSV or in the ICs.
AB - The development of 3D-silicon integrated circuits is an increasing demand especially regarding to advanced 3D-packages and high performance applications, with the intend to miniaturize and to reduce costs. Through-silicon-vias (TSV), interconnects and landing pads have a strong mismatch in proportions. Due to high temperature as well as high applied currents, the reliability of the systems and components is affected by thermal and thermal-electrical loads. The induced stress leads to degradation effects like electro- and thermomigration (EM, TM). Mismatch in coefficient of thermal expansion (CTE) are causing mechanical induced stress during the manufacturing process. This can lead to failure mechanisms like delamination and cracking around the TSV or in the ICs.
KW - 3-D integration
KW - delamination
KW - migration effects
KW - reliability
KW - simulation
KW - TSV
UR - http://www.scopus.com/inward/record.url?scp=84904559669&partnerID=8YFLogxK
U2 - 10.1109/lascas.2014.6820324
DO - 10.1109/lascas.2014.6820324
M3 - Conference contribution
AN - SCOPUS:84904559669
SN - 9781479925070
BT - 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings
PB - IEEE Computer Society
T2 - 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014
Y2 - 25 February 2014 through 28 February 2014
ER -