TY - JOUR

T1 - Reuse of Substrate Wafers for the Porous Silicon Layer Transfer

AU - Steckenreiter, Verena

AU - Hensen, Jan

AU - Knorr, Alwina

AU - Kajari-Schroder, Sarah

AU - Brendel, Rolf

N1 - Acknowledgements: The authors would like to thank A. Albu and Dr. W. Appel at IMS CHIPS for epitaxial depositions. They would also like to thank Dr. B. Lim for valuable help with the boron–oxygen analysis and Dr. R. Niepelt for the profilometric mappings. Furthermore, they would like to thank Dr. E. Garralaga Rojas, Dr. F. Haase, M. Nese, Dr. D. Nilsen Wright, and Dr. A. Bentzen for fruitful discussions.

PY - 2016/5

Y1 - 2016/5

N2 - The reuse of the silicon substrate is a key component in the kerfless-porous-silicon-based wafering process. Starting with a boron-doped p+-type substrate, a porous double layer is created, reorganized in a hydrogen bake, and then serves as a substrate for silicon homoepitaxy. After lift-off, the silicon substrate is wet chemically reconditioned and reporosified to serve again as a substrate for epitaxial layer deposition. We reduce the substrate consumption per cycle to 5 ± 0.3 μm/side and demonstrate 14 uses on a 6-in wafer. We investigate the impact of the reuse sequence on the epitaxial layer quality by carrier lifetime measurements. Starting with the third reuse, a pattern becomes visible in lifetime mappings. We observe a degradation of the minority carrier lifetime from 15 to 7 μs after 13 reuses.

AB - The reuse of the silicon substrate is a key component in the kerfless-porous-silicon-based wafering process. Starting with a boron-doped p+-type substrate, a porous double layer is created, reorganized in a hydrogen bake, and then serves as a substrate for silicon homoepitaxy. After lift-off, the silicon substrate is wet chemically reconditioned and reporosified to serve again as a substrate for epitaxial layer deposition. We reduce the substrate consumption per cycle to 5 ± 0.3 μm/side and demonstrate 14 uses on a 6-in wafer. We investigate the impact of the reuse sequence on the epitaxial layer quality by carrier lifetime measurements. Starting with the third reuse, a pattern becomes visible in lifetime mappings. We observe a degradation of the minority carrier lifetime from 15 to 7 μs after 13 reuses.

KW - Carrier lifetime

KW - epitaxial layer

KW - layer transfer

KW - porous silicon (PSI) process

KW - Substrate reuse

UR - http://www.scopus.com/inward/record.url?scp=84979724287&partnerID=8YFLogxK

U2 - 10.1109/JPHOTOV.2016.2545406

DO - 10.1109/JPHOTOV.2016.2545406

M3 - Article

AN - SCOPUS:84979724287

VL - 6

SP - 783

EP - 790

JO - IEEE journal of photovoltaics

JF - IEEE journal of photovoltaics

SN - 2156-3381

IS - 3

M1 - 7452343

ER -