TY - JOUR

T1 - Resource-awareness on heterogeneous MPSoCs for image processing

AU - Paul, Johny

AU - Stechele, Walter

AU - Oechslein, Benjamin

AU - Erhardt, Christoph

AU - Schedel, Jens

AU - Lohmann, Daniel

AU - Schröder-Preikschat, Wolfgang

AU - Kröhnert, Manfred

AU - Asfour, Tamim

AU - Sousa, Éricles

AU - Lari, Vahid

AU - Hannig, Frank

AU - Teich, Jürgen

AU - Grudnitsky, Artjom

AU - Bauer, Lars

AU - Henkel, Jörg

PY - 2015/11/6

Y1 - 2015/11/6

N2 - Multiprocessor system-on-chip (MPSoC) designs offer a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions. On-chip MPPAs can be used to accelerate low-level image-processing algorithms with massive inherent parallelism. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, among others. The conventional approach used for programming heterogeneous MPSoCs results in a static mapping of various parts of the application to different PE types, based on the nature of the algorithm and the structure of the PEs. Yet, such a mapping scheme independent of the instantaneous load on the PEs may lead to under-utilization of some type of PEs while overloading others. In this work, we investigate the benefits of using a heterogeneous MPSoC for accelerating various stages within a real-world image-processing algorithm for object-recognition. A case study demonstrates that a resource-aware programming model called Invasive Computing helps to improve the throughput and worst observed latency of the application program, by dynamically mapping applications to different types of PEs available on a heterogeneous MPSoC.

AB - Multiprocessor system-on-chip (MPSoC) designs offer a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions. On-chip MPPAs can be used to accelerate low-level image-processing algorithms with massive inherent parallelism. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, among others. The conventional approach used for programming heterogeneous MPSoCs results in a static mapping of various parts of the application to different PE types, based on the nature of the algorithm and the structure of the PEs. Yet, such a mapping scheme independent of the instantaneous load on the PEs may lead to under-utilization of some type of PEs while overloading others. In this work, we investigate the benefits of using a heterogeneous MPSoC for accelerating various stages within a real-world image-processing algorithm for object-recognition. A case study demonstrates that a resource-aware programming model called Invasive Computing helps to improve the throughput and worst observed latency of the application program, by dynamically mapping applications to different types of PEs available on a heterogeneous MPSoC.

KW - Computer vision

KW - Heterogeneous processor

KW - Image processing

KW - Invasive Computing

KW - MPSoC

KW - Resource awareness

UR - http://www.scopus.com/inward/record.url?scp=84948454282&partnerID=8YFLogxK

U2 - 10.1016/j.sysarc.2015.09.002

DO - 10.1016/j.sysarc.2015.09.002

M3 - Article

AN - SCOPUS:84948454282

VL - 61

SP - 668

EP - 680

JO - Journal of Systems Architecture

JF - Journal of Systems Architecture

SN - 1383-7621

IS - 10

ER -