Details
| Titel in Übersetzung | Rapid Prototyping of Video Processing Schemes |
|---|---|
| Originalsprache | Deutsch |
| Seiten (von - bis) | 5-9 |
| Seitenumfang | 5 |
| Fachzeitschrift | it - Information Technology |
| Jahrgang | 42 |
| Ausgabenummer | 3 |
| Publikationsstatus | Veröffentlicht - 1 März 2000 |
Abstract
The implementation of video processing schemes, for example CCITT visual telephony (H.263) or MPEG, demands the choice of appropriate algorithms and architectural alternatives. To determine the influence of algorithm and circuit parameters on image quality, it is desireable to support a designer in his decision at an early design stage. A traditionally used software simulation can not be used for verification of long video sequences. Therefore, a flexible real-time hardware prototyping of video processing schemes is mandatory, which allows high throughput rates. Hence, the "Video and Image Processing Emulation System"(VIPES) has been built, a rapid prototyping system for complete video processing schemes. VIPES is based on a commercial FPGA emulation platform. To meet real-time constraints, we have extended this emulation environment by dedicated video interfaces, efficient flexible FPGA macros and software. As an example for a complete scheme, results for the implementation of a H.263 video codec are presented. The feasibility of the rapidprototyping system is shown for a two-dimensional discrete cosine transform, resulting in a reduction of 4 8 % in terms of FPGA resources, and 8 0 % of compilation time.
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in: it - Information Technology, Jahrgang 42, Nr. 3, 01.03.2000, S. 5-9.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Rapid Prototyping von Videosignalverarbeitungsverfahren
AU - Reuter, Carsten
AU - Kropp, Holger
AU - Pirsch, Peter
PY - 2000/3/1
Y1 - 2000/3/1
N2 - The implementation of video processing schemes, for example CCITT visual telephony (H.263) or MPEG, demands the choice of appropriate algorithms and architectural alternatives. To determine the influence of algorithm and circuit parameters on image quality, it is desireable to support a designer in his decision at an early design stage. A traditionally used software simulation can not be used for verification of long video sequences. Therefore, a flexible real-time hardware prototyping of video processing schemes is mandatory, which allows high throughput rates. Hence, the "Video and Image Processing Emulation System"(VIPES) has been built, a rapid prototyping system for complete video processing schemes. VIPES is based on a commercial FPGA emulation platform. To meet real-time constraints, we have extended this emulation environment by dedicated video interfaces, efficient flexible FPGA macros and software. As an example for a complete scheme, results for the implementation of a H.263 video codec are presented. The feasibility of the rapidprototyping system is shown for a two-dimensional discrete cosine transform, resulting in a reduction of 4 8 % in terms of FPGA resources, and 8 0 % of compilation time.
AB - The implementation of video processing schemes, for example CCITT visual telephony (H.263) or MPEG, demands the choice of appropriate algorithms and architectural alternatives. To determine the influence of algorithm and circuit parameters on image quality, it is desireable to support a designer in his decision at an early design stage. A traditionally used software simulation can not be used for verification of long video sequences. Therefore, a flexible real-time hardware prototyping of video processing schemes is mandatory, which allows high throughput rates. Hence, the "Video and Image Processing Emulation System"(VIPES) has been built, a rapid prototyping system for complete video processing schemes. VIPES is based on a commercial FPGA emulation platform. To meet real-time constraints, we have extended this emulation environment by dedicated video interfaces, efficient flexible FPGA macros and software. As an example for a complete scheme, results for the implementation of a H.263 video codec are presented. The feasibility of the rapidprototyping system is shown for a two-dimensional discrete cosine transform, resulting in a reduction of 4 8 % in terms of FPGA resources, and 8 0 % of compilation time.
UR - http://www.scopus.com/inward/record.url?scp=85117235757&partnerID=8YFLogxK
U2 - 10.1524/itit.2000.42.3.5
DO - 10.1524/itit.2000.42.3.5
M3 - Artikel
AN - SCOPUS:85117235757
VL - 42
SP - 5
EP - 9
JO - it - Information Technology
JF - it - Information Technology
SN - 1611-2776
IS - 3
ER -