Details
Originalsprache | Englisch |
---|---|
Titel des Sammelwerks | 1990 Proc Int Conf Wafer Scale Integr |
Herausgeber/-innen | Joe Brewer, Michael J. Little |
Seiten | 288-297 |
Seitenumfang | 10 |
Publikationsstatus | Veröffentlicht - 1990 |
Veranstaltung | 1990 International Conference on Wafer Scale Integration - San Francisco, USA / Vereinigte Staaten Dauer: 23 Jan. 1990 → 25 Jan. 1990 |
Publikationsreihe
Name | 1990 Proc Int Conf Wafer Scale Integr |
---|
Abstract
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Allgemeiner Maschinenbau
Zitieren
- Standard
- Harvard
- Apa
- Vancouver
- BibTex
- RIS
1990 Proc Int Conf Wafer Scale Integr. Hrsg. / Joe Brewer; Michael J. Little. 1990. S. 288-297 (1990 Proc Int Conf Wafer Scale Integr).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Power distribution strategies based on current estimation and simulation of lossy transmission lines in conjunction with power isolation circuits
AU - Jagau, U.
AU - Dyck, K. P.
AU - Grabinski, H.
AU - Iden, H. J.
AU - Kuboschek, M.
PY - 1990
Y1 - 1990
N2 - Investigations have shown that the layout of power lines and isolation circuits as well as the modules' circuit switching has a large influence on the behavior of the whole system. A current estimation strategy for the calculation of the module current consumption in CMOS technology is investigated. The electrical behavior of losses in signal and power lines is taken into account. An efficient current estimation is introduced with a new program-SIMCURRENT. Another program carries out analog circuit simulations including the modelling of coupled lossy transmission lines. Fast and accurate estimates of the I/sub dd/-current are carried out by SIMCURRENT. Simulations-often not possible with classical circuit analysis programs-were made with the program LISM. Regarding monolithic systems, one must include power isolation circuits in the power rail system. A proper layout of the global supply network (not using the lowest resistive layout) is proposed.
AB - Investigations have shown that the layout of power lines and isolation circuits as well as the modules' circuit switching has a large influence on the behavior of the whole system. A current estimation strategy for the calculation of the module current consumption in CMOS technology is investigated. The electrical behavior of losses in signal and power lines is taken into account. An efficient current estimation is introduced with a new program-SIMCURRENT. Another program carries out analog circuit simulations including the modelling of coupled lossy transmission lines. Fast and accurate estimates of the I/sub dd/-current are carried out by SIMCURRENT. Simulations-often not possible with classical circuit analysis programs-were made with the program LISM. Regarding monolithic systems, one must include power isolation circuits in the power rail system. A proper layout of the global supply network (not using the lowest resistive layout) is proposed.
UR - http://www.scopus.com/inward/record.url?scp=0025207877&partnerID=8YFLogxK
U2 - 10.1109/ICWSI.1990.63912
DO - 10.1109/ICWSI.1990.63912
M3 - Conference contribution
AN - SCOPUS:0025207877
SN - 0818690135
T3 - 1990 Proc Int Conf Wafer Scale Integr
SP - 288
EP - 297
BT - 1990 Proc Int Conf Wafer Scale Integr
A2 - Brewer, Joe
A2 - Little, Michael J.
T2 - 1990 International Conference on Wafer Scale Integration
Y2 - 23 January 1990 through 25 January 1990
ER -