Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

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  • Rheinisch-Westfälische Technische Hochschule Aachen (RWTH)
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Details

OriginalspracheEnglisch
Titel des SammelwerksComputer Systems
UntertitelArchitectures, Modeling, and Simulation
Herausgeber/-innenAndy D. Pimentel, Stamatis Vassiliadis
ErscheinungsortBerlin
Herausgeber (Verlag)Springer Verlag
Seiten484-493
Seitenumfang10
ISBN (elektronisch)9783540277767
ISBN (Print)3540223770, 9783540223771
PublikationsstatusVeröffentlicht - 2004
Extern publiziertJa

Publikationsreihe

NameLecture Notes in Computer Science (LNCS)
Band3133
ISSN (Print)0302-9743
ISSN (elektronisch)1611-3349

Abstract

Design space exploration (DSE) for heterogeneous Systems on Chip (SoCs) is a key issue as today's SoC complexity is steadily increasing. Methods for the estimation of implementation specific performance and cost features on all levels of design have to be developed. This contribution proposes an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze onchip communication which is of increasing importance. In order to demonstrate the suitability of this approach the on-chip communication structure of two examples featuring typical SoC communication conflicts like competition for common communication resources have been studied. A modern heterogeneous DSP and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.

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Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets. / Blume, Holger; Von Sydow, Thorsten; Noll, Tobias G.
Computer Systems: Architectures, Modeling, and Simulation. Hrsg. / Andy D. Pimentel; Stamatis Vassiliadis. Berlin: Springer Verlag, 2004. S. 484-493 (Lecture Notes in Computer Science (LNCS); Band 3133).

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

Blume, H, Von Sydow, T & Noll, TG 2004, Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets. in AD Pimentel & S Vassiliadis (Hrsg.), Computer Systems: Architectures, Modeling, and Simulation. Lecture Notes in Computer Science (LNCS), Bd. 3133, Springer Verlag, Berlin, S. 484-493. https://doi.org/10.1007/978-3-540-27776-7_50
Blume, H., Von Sydow, T., & Noll, T. G. (2004). Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets. In A. D. Pimentel, & S. Vassiliadis (Hrsg.), Computer Systems: Architectures, Modeling, and Simulation (S. 484-493). (Lecture Notes in Computer Science (LNCS); Band 3133). Springer Verlag. https://doi.org/10.1007/978-3-540-27776-7_50
Blume H, Von Sydow T, Noll TG. Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets. in Pimentel AD, Vassiliadis S, Hrsg., Computer Systems: Architectures, Modeling, and Simulation. Berlin: Springer Verlag. 2004. S. 484-493. (Lecture Notes in Computer Science (LNCS)). doi: 10.1007/978-3-540-27776-7_50
Blume, Holger ; Von Sydow, Thorsten ; Noll, Tobias G. / Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets. Computer Systems: Architectures, Modeling, and Simulation. Hrsg. / Andy D. Pimentel ; Stamatis Vassiliadis. Berlin : Springer Verlag, 2004. S. 484-493 (Lecture Notes in Computer Science (LNCS)).
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@inproceedings{878e5058e3734586974c4113d9dfbaf8,
title = "Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets",
abstract = "Design space exploration (DSE) for heterogeneous Systems on Chip (SoCs) is a key issue as today's SoC complexity is steadily increasing. Methods for the estimation of implementation specific performance and cost features on all levels of design have to be developed. This contribution proposes an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze onchip communication which is of increasing importance. In order to demonstrate the suitability of this approach the on-chip communication structure of two examples featuring typical SoC communication conflicts like competition for common communication resources have been studied. A modern heterogeneous DSP and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.",
author = "Holger Blume and {Von Sydow}, Thorsten and Noll, {Tobias G.}",
year = "2004",
doi = "10.1007/978-3-540-27776-7_50",
language = "English",
isbn = "3540223770",
series = "Lecture Notes in Computer Science (LNCS)",
publisher = "Springer Verlag",
pages = "484--493",
editor = "Pimentel, {Andy D.} and Stamatis Vassiliadis",
booktitle = "Computer Systems",
address = "Germany",

}

Download

TY - GEN

T1 - Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets

AU - Blume, Holger

AU - Von Sydow, Thorsten

AU - Noll, Tobias G.

PY - 2004

Y1 - 2004

N2 - Design space exploration (DSE) for heterogeneous Systems on Chip (SoCs) is a key issue as today's SoC complexity is steadily increasing. Methods for the estimation of implementation specific performance and cost features on all levels of design have to be developed. This contribution proposes an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze onchip communication which is of increasing importance. In order to demonstrate the suitability of this approach the on-chip communication structure of two examples featuring typical SoC communication conflicts like competition for common communication resources have been studied. A modern heterogeneous DSP and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.

AB - Design space exploration (DSE) for heterogeneous Systems on Chip (SoCs) is a key issue as today's SoC complexity is steadily increasing. Methods for the estimation of implementation specific performance and cost features on all levels of design have to be developed. This contribution proposes an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze onchip communication which is of increasing importance. In order to demonstrate the suitability of this approach the on-chip communication structure of two examples featuring typical SoC communication conflicts like competition for common communication resources have been studied. A modern heterogeneous DSP and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.

UR - http://www.scopus.com/inward/record.url?scp=35048855589&partnerID=8YFLogxK

U2 - 10.1007/978-3-540-27776-7_50

DO - 10.1007/978-3-540-27776-7_50

M3 - Conference contribution

AN - SCOPUS:35048855589

SN - 3540223770

SN - 9783540223771

T3 - Lecture Notes in Computer Science (LNCS)

SP - 484

EP - 493

BT - Computer Systems

A2 - Pimentel, Andy D.

A2 - Vassiliadis, Stamatis

PB - Springer Verlag

CY - Berlin

ER -

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