Details
| Originalsprache | Englisch |
|---|---|
| Seiten | 169-174 |
| Seitenumfang | 6 |
| Publikationsstatus | Veröffentlicht - 2018 |
| Veranstaltung | 16. GMM/ITG-Fachtagung ANALOG 2018: Meet Your CAD Guy / Meet Your Designer - 16th GMM/ITG Symposium ANALOG 2018: Meet Your CAD Guy/Meet Your Designer - Munchen/Neubiberg, Deutschland Dauer: 13 Sept. 2018 → 14 Sept. 2018 |
Konferenz
| Konferenz | 16. GMM/ITG-Fachtagung ANALOG 2018: Meet Your CAD Guy / Meet Your Designer - 16th GMM/ITG Symposium ANALOG 2018: Meet Your CAD Guy/Meet Your Designer |
|---|---|
| Land/Gebiet | Deutschland |
| Ort | Munchen/Neubiberg |
| Zeitraum | 13 Sept. 2018 → 14 Sept. 2018 |
Abstract
Since processor speeds have plateaued in recent years, other avenues need to be explored to speed up Electronic Design Automation (EDA) applications in order to keep pace with the growing complexity of VLSI designs. The ubiquity of multicore processors makes parallelization an obvious approach for achieving further performance improvements. However, fully realizing the potential provided by many-core systems requires the algorithms to be carefully designed to avoid bottlenecks. The detailed routing step can take a lot of time and therefore is a good candidate for performance improvements. However, the necessity of generating legal routing results makes it challenging to scale to lots of processing cores due to the necessary communication overhead. This paper gives an overview on different approaches to the problem. Furthermore, we identify the core problems of different approaches.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Hardware und Architektur
- Informatik (insg.)
- Signalverarbeitung
- Werkstoffwissenschaften (insg.)
- Oberflächen, Beschichtungen und Folien
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2018. 169-174 Beitrag in 16. GMM/ITG-Fachtagung ANALOG 2018: Meet Your CAD Guy / Meet Your Designer - 16th GMM/ITG Symposium ANALOG 2018: Meet Your CAD Guy/Meet Your Designer, Munchen/Neubiberg, Deutschland.
Publikation: Konferenzbeitrag › Paper › Forschung › Peer-Review
}
TY - CONF
T1 - Parallelization strategies for the detailed routing step
AU - Bredthauer, Björn
AU - Olbrich, Markus
AU - Barke, Erich
N1 - Publisher Copyright: © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach Copyright: Copyright 2021 Elsevier B.V., All rights reserved.
PY - 2018
Y1 - 2018
N2 - Since processor speeds have plateaued in recent years, other avenues need to be explored to speed up Electronic Design Automation (EDA) applications in order to keep pace with the growing complexity of VLSI designs. The ubiquity of multicore processors makes parallelization an obvious approach for achieving further performance improvements. However, fully realizing the potential provided by many-core systems requires the algorithms to be carefully designed to avoid bottlenecks. The detailed routing step can take a lot of time and therefore is a good candidate for performance improvements. However, the necessity of generating legal routing results makes it challenging to scale to lots of processing cores due to the necessary communication overhead. This paper gives an overview on different approaches to the problem. Furthermore, we identify the core problems of different approaches.
AB - Since processor speeds have plateaued in recent years, other avenues need to be explored to speed up Electronic Design Automation (EDA) applications in order to keep pace with the growing complexity of VLSI designs. The ubiquity of multicore processors makes parallelization an obvious approach for achieving further performance improvements. However, fully realizing the potential provided by many-core systems requires the algorithms to be carefully designed to avoid bottlenecks. The detailed routing step can take a lot of time and therefore is a good candidate for performance improvements. However, the necessity of generating legal routing results makes it challenging to scale to lots of processing cores due to the necessary communication overhead. This paper gives an overview on different approaches to the problem. Furthermore, we identify the core problems of different approaches.
UR - http://www.scopus.com/inward/record.url?scp=85099535023&partnerID=8YFLogxK
M3 - Paper
AN - SCOPUS:85099535023
SP - 169
EP - 174
T2 - 16. GMM/ITG-Fachtagung ANALOG 2018: Meet Your CAD Guy / Meet Your Designer - 16th GMM/ITG Symposium ANALOG 2018: Meet Your CAD Guy/Meet Your Designer
Y2 - 13 September 2018 through 14 September 2018
ER -