Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 562-565 |
| Seitenumfang | 4 |
| Fachzeitschrift | Proceedings - IEEE International Symposium on Circuits and Systems |
| Jahrgang | 1 |
| Publikationsstatus | Veröffentlicht - 1995 |
| Veranstaltung | The 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995. Part 3 (of 3) - Seattle, USA / Vereinigte Staaten Dauer: 30 Apr. 1995 → 3 Mai 1995 |
Abstract
For the design of a highly parallel programmable videosignal processor, the parallelization resources and characteristic properties of image processing algorithms have been analyzed. Basing on the resulting algorithmic requirements, an architecture for a reduced instruction set processor with parallel data paths, called HiPAR-DSP has been deduced. The processor consists of 4 or 16 parallel data paths with local data caches, coupled by a shared memory with matrix type data access. Control, memory and arithmetic architecture of the processor are properly balanced and adapted to the control flow and data access patterns of algorithms, resulting in a remarkable high sustained processing power for a broad spectrum of image processing algorithms.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Proceedings - IEEE International Symposium on Circuits and Systems, Jahrgang 1, 1995, S. 562-565.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor
AU - Pirsch, Peter
AU - Kneip, Johannes
AU - Roenner, Karsten
PY - 1995
Y1 - 1995
N2 - For the design of a highly parallel programmable videosignal processor, the parallelization resources and characteristic properties of image processing algorithms have been analyzed. Basing on the resulting algorithmic requirements, an architecture for a reduced instruction set processor with parallel data paths, called HiPAR-DSP has been deduced. The processor consists of 4 or 16 parallel data paths with local data caches, coupled by a shared memory with matrix type data access. Control, memory and arithmetic architecture of the processor are properly balanced and adapted to the control flow and data access patterns of algorithms, resulting in a remarkable high sustained processing power for a broad spectrum of image processing algorithms.
AB - For the design of a highly parallel programmable videosignal processor, the parallelization resources and characteristic properties of image processing algorithms have been analyzed. Basing on the resulting algorithmic requirements, an architecture for a reduced instruction set processor with parallel data paths, called HiPAR-DSP has been deduced. The processor consists of 4 or 16 parallel data paths with local data caches, coupled by a shared memory with matrix type data access. Control, memory and arithmetic architecture of the processor are properly balanced and adapted to the control flow and data access patterns of algorithms, resulting in a remarkable high sustained processing power for a broad spectrum of image processing algorithms.
UR - http://www.scopus.com/inward/record.url?scp=0029203330&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0029203330
VL - 1
SP - 562
EP - 565
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
T2 - The 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995. Part 3 (of 3)
Y2 - 30 April 1995 through 3 May 1995
ER -