Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 316-319 |
| Seitenumfang | 4 |
| Fachzeitschrift | Proceedings - IEEE International Symposium on Circuits and Systems |
| Jahrgang | 4 |
| Publikationsstatus | Veröffentlicht - 1996 |
| Veranstaltung | 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, USA / Vereinigte Staaten Dauer: 12 Mai 1996 → 15 Mai 1996 |
Abstract
The efficient implementation of algorithms with irregular data access or control-flow on a parallel SIMD processor requires specific architectural measures. This paper demonstrates the parallelization of medium-level algorithms on the HiPAR-DSP, a programmable RISC processor for real-time image processing with 4 or 16 parallel data paths. We show the efficient use of memory and ASIMD control capabilities of the processor for the parallel execution of a memory efficient Huffman decoding algorithm. Performance figures for a selection of further medium level algorithms are given, demonstrating that even a SIMD architecture can obtain high utilization for algorithms with data dependent control flow.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Proceedings - IEEE International Symposium on Circuits and Systems, Jahrgang 4, 1996, S. 316-319.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Parallel implementation of medium level algorithms on a monolithic ASIMD multiprocessor
AU - Kneip, Johannes
AU - Ohmacht, Martin
AU - Wittenburg, Jens Peter
AU - Pirsch, Peter
PY - 1996
Y1 - 1996
N2 - The efficient implementation of algorithms with irregular data access or control-flow on a parallel SIMD processor requires specific architectural measures. This paper demonstrates the parallelization of medium-level algorithms on the HiPAR-DSP, a programmable RISC processor for real-time image processing with 4 or 16 parallel data paths. We show the efficient use of memory and ASIMD control capabilities of the processor for the parallel execution of a memory efficient Huffman decoding algorithm. Performance figures for a selection of further medium level algorithms are given, demonstrating that even a SIMD architecture can obtain high utilization for algorithms with data dependent control flow.
AB - The efficient implementation of algorithms with irregular data access or control-flow on a parallel SIMD processor requires specific architectural measures. This paper demonstrates the parallelization of medium-level algorithms on the HiPAR-DSP, a programmable RISC processor for real-time image processing with 4 or 16 parallel data paths. We show the efficient use of memory and ASIMD control capabilities of the processor for the parallel execution of a memory efficient Huffman decoding algorithm. Performance figures for a selection of further medium level algorithms are given, demonstrating that even a SIMD architecture can obtain high utilization for algorithms with data dependent control flow.
UR - http://www.scopus.com/inward/record.url?scp=0029697178&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0029697178
VL - 4
SP - 316
EP - 319
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
T2 - 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4)
Y2 - 12 May 1996 through 15 May 1996
ER -