Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 2024 IEEE Applied Power Electronics Conference and Exposition |
| Untertitel | APEC |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| Seiten | 2409-2414 |
| Seitenumfang | 6 |
| ISBN (elektronisch) | 9798350316643 |
| ISBN (Print) | 979-8-3503-1665-0 |
| Publikationsstatus | Veröffentlicht - 2024 |
| Veranstaltung | 39th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2024 - Long Beach, USA / Vereinigte Staaten Dauer: 25 Feb. 2024 → 29 Feb. 2024 |
Abstract
Despite monolithic integration of GaN gate drivers with the power stage, some parasitic gate loop inductance remains, including connections to off-chip decoupling capacitors. On-chip capacitors, however, complicate the gate loop design by adding another pole to the system. An LC-RC resonant tank replaces the conventional RLC model, which is insufficient. Ultra-low ESL decoupling using chip-scale silicon capacitors bonded directly to the GaN-IC is identified as most effective by measurements for PCB and bonded MLCC and SiCap gate loop decoupling. A voltage-tuning technique-based gate driver, implemented on a GaN-IC, is applied to adapt to the remaining loop inductance and reduce critical overshoot while ensuring fast switching.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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2024 IEEE Applied Power Electronics Conference and Exposition: APEC . Institute of Electrical and Electronics Engineers Inc., 2024. S. 2409-2414.
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Overshoot Prevention in Monolithic GaN by Ultra-Low ESL Gate Loop Design Using Chip-Scale Capacitors and Gate Driver Pull-Up Path Tuning Technique
AU - Deneke, Niklas
AU - Wicht, Bernhard
N1 - Publisher Copyright: © 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Despite monolithic integration of GaN gate drivers with the power stage, some parasitic gate loop inductance remains, including connections to off-chip decoupling capacitors. On-chip capacitors, however, complicate the gate loop design by adding another pole to the system. An LC-RC resonant tank replaces the conventional RLC model, which is insufficient. Ultra-low ESL decoupling using chip-scale silicon capacitors bonded directly to the GaN-IC is identified as most effective by measurements for PCB and bonded MLCC and SiCap gate loop decoupling. A voltage-tuning technique-based gate driver, implemented on a GaN-IC, is applied to adapt to the remaining loop inductance and reduce critical overshoot while ensuring fast switching.
AB - Despite monolithic integration of GaN gate drivers with the power stage, some parasitic gate loop inductance remains, including connections to off-chip decoupling capacitors. On-chip capacitors, however, complicate the gate loop design by adding another pole to the system. An LC-RC resonant tank replaces the conventional RLC model, which is insufficient. Ultra-low ESL decoupling using chip-scale silicon capacitors bonded directly to the GaN-IC is identified as most effective by measurements for PCB and bonded MLCC and SiCap gate loop decoupling. A voltage-tuning technique-based gate driver, implemented on a GaN-IC, is applied to adapt to the remaining loop inductance and reduce critical overshoot while ensuring fast switching.
KW - Decoupling
KW - GaN-IC
KW - Gate Driver
KW - Gate Loop
KW - MLCC
KW - Monolithic GaN
KW - SiCap
UR - http://www.scopus.com/inward/record.url?scp=85192777836&partnerID=8YFLogxK
U2 - 10.1109/APEC48139.2024.10509192
DO - 10.1109/APEC48139.2024.10509192
M3 - Conference contribution
AN - SCOPUS:85192777836
SN - 979-8-3503-1665-0
SP - 2409
EP - 2414
BT - 2024 IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 39th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2024
Y2 - 25 February 2024 through 29 February 2024
ER -