Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 2017 IEEE Applied Power Electronics Conference and Exposition (APEC) |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| Seiten | 3564-3569 |
| Seitenumfang | 6 |
| ISBN (elektronisch) | 9781509053667 |
| ISBN (Print) | 9781509053667 |
| Publikationsstatus | Veröffentlicht - 2017 |
| Extern publiziert | Ja |
| Veranstaltung | 32nd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2017 - Tampa, USA / Vereinigte Staaten Dauer: 26 März 2017 → 30 März 2017 |
Publikationsreihe
| Name | Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC |
|---|---|
| ISSN (elektronisch) | 2470-6647 |
Abstract
In a digitally controlled slope shaping system, reliable detection of both voltage and current slope is required to enable a closed-loop control for various power switches independent of system parameters. In most state-of-the-art works, this is realized by monitoring the absolute voltage and current values. Better accuracy at lower DC power loss is achieved by sensing techniques for a reliable passive detection, which is achieved through avoiding DC paths from the high voltage network into the sensing network. Using a high-speed analog-to-digital converter, the whole waveform of the transient derivative can be stored digitally and prepared for a predictive cycle-by-cycle regulation, without requiring high-precision digital differentiation algorithms. To gain an accurate representation of the voltage and current derivative waveforms, system parasitics are investigated and classified in three sections: (1) component parasitics, which are identified by s-parameter measurements and extraction of equivalent circuit models, (2) PCB design issues related to the sensing circuit, and (3) interconnections between adjacent boards. The contribution of this paper is an optimized sensing network on the basis of the experimental study supporting fast transition slopes up to 100 V/ns and 1 A/ns and beyond, making the sensing technique attractive for slope shaping of fast switching devices like modern generation IGBTs, CoolMOSTM and SiC mosfets. Measurements of the optimized dv/dt and di/dt setups are demonstrated for a hard switched IGBT power stage.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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2017 IEEE Applied Power Electronics Conference and Exposition (APEC). Institute of Electrical and Electronics Engineers Inc., 2017. S. 3564-3569 7931209 (Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Optimized dv/dt, di/dt Sensing for a Digitally Controlled Slope Shaping Gate Driver
AU - Groeger, Johannes
AU - Schindler, Alexis
AU - Wicht, Bernhard
AU - Norling, Karl
N1 - Publisher Copyright: © 2017 IEEE. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2017
Y1 - 2017
N2 - In a digitally controlled slope shaping system, reliable detection of both voltage and current slope is required to enable a closed-loop control for various power switches independent of system parameters. In most state-of-the-art works, this is realized by monitoring the absolute voltage and current values. Better accuracy at lower DC power loss is achieved by sensing techniques for a reliable passive detection, which is achieved through avoiding DC paths from the high voltage network into the sensing network. Using a high-speed analog-to-digital converter, the whole waveform of the transient derivative can be stored digitally and prepared for a predictive cycle-by-cycle regulation, without requiring high-precision digital differentiation algorithms. To gain an accurate representation of the voltage and current derivative waveforms, system parasitics are investigated and classified in three sections: (1) component parasitics, which are identified by s-parameter measurements and extraction of equivalent circuit models, (2) PCB design issues related to the sensing circuit, and (3) interconnections between adjacent boards. The contribution of this paper is an optimized sensing network on the basis of the experimental study supporting fast transition slopes up to 100 V/ns and 1 A/ns and beyond, making the sensing technique attractive for slope shaping of fast switching devices like modern generation IGBTs, CoolMOSTM and SiC mosfets. Measurements of the optimized dv/dt and di/dt setups are demonstrated for a hard switched IGBT power stage.
AB - In a digitally controlled slope shaping system, reliable detection of both voltage and current slope is required to enable a closed-loop control for various power switches independent of system parameters. In most state-of-the-art works, this is realized by monitoring the absolute voltage and current values. Better accuracy at lower DC power loss is achieved by sensing techniques for a reliable passive detection, which is achieved through avoiding DC paths from the high voltage network into the sensing network. Using a high-speed analog-to-digital converter, the whole waveform of the transient derivative can be stored digitally and prepared for a predictive cycle-by-cycle regulation, without requiring high-precision digital differentiation algorithms. To gain an accurate representation of the voltage and current derivative waveforms, system parasitics are investigated and classified in three sections: (1) component parasitics, which are identified by s-parameter measurements and extraction of equivalent circuit models, (2) PCB design issues related to the sensing circuit, and (3) interconnections between adjacent boards. The contribution of this paper is an optimized sensing network on the basis of the experimental study supporting fast transition slopes up to 100 V/ns and 1 A/ns and beyond, making the sensing technique attractive for slope shaping of fast switching devices like modern generation IGBTs, CoolMOSTM and SiC mosfets. Measurements of the optimized dv/dt and di/dt setups are demonstrated for a hard switched IGBT power stage.
UR - http://www.scopus.com/inward/record.url?scp=85019979633&partnerID=8YFLogxK
U2 - 10.1109/APEC.2017.7931209
DO - 10.1109/APEC.2017.7931209
M3 - Conference contribution
AN - SCOPUS:85019979633
SN - 9781509053667
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 3564
EP - 3569
BT - 2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 32nd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2017
Y2 - 26 March 2017 through 30 March 2017
ER -