Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 1019-1029 |
| Seitenumfang | 11 |
| Fachzeitschrift | Journal of Systems Architecture |
| Jahrgang | 54 |
| Ausgabenummer | 11 |
| Publikationsstatus | Veröffentlicht - 6 Apr. 2008 |
| Extern publiziert | Ja |
Abstract
In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For parallelization issues the OpenMP programming model has been used which can be efficiently applied on C-level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Software
- Informatik (insg.)
- Hardware und Architektur
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in: Journal of Systems Architecture, Jahrgang 54, Nr. 11, 06.04.2008, S. 1019-1029.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - OpenMP-based parallelization on an MPCore multiprocessor platform
T2 - A performance and power analysis
AU - Blume, H.
AU - Livonius, J. von
AU - Rotenberg, L.
AU - Noll, T. G.
AU - Bothe, H.
AU - Brakensiek, J.
PY - 2008/4/6
Y1 - 2008/4/6
N2 - In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For parallelization issues the OpenMP programming model has been used which can be efficiently applied on C-level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.
AB - In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For parallelization issues the OpenMP programming model has been used which can be efficiently applied on C-level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.
KW - Multicore processors
KW - Optimization
KW - Parallelization
KW - Power estimation
UR - http://www.scopus.com/inward/record.url?scp=52949153284&partnerID=8YFLogxK
U2 - 10.1016/j.sysarc.2008.04.001
DO - 10.1016/j.sysarc.2008.04.001
M3 - Article
AN - SCOPUS:52949153284
VL - 54
SP - 1019
EP - 1029
JO - Journal of Systems Architecture
JF - Journal of Systems Architecture
SN - 1383-7621
IS - 11
ER -