On the design of scalable massively parallel CRC circuits

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

Autoren

  • Konstantin Septinus
  • Thuyen Le
  • Ulrich Mayer
  • Peter Pirsch

Organisationseinheiten

Externe Organisationen

  • IBM
Forschungs-netzwerk anzeigen

Details

OriginalspracheEnglisch
Titel des SammelwerksICECS 2007
Untertitel14th IEEE International Conference on Electronics, Circuits and Systems
Seiten142-145
Seitenumfang4
PublikationsstatusVeröffentlicht - 2007
Veranstaltung14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Marokko
Dauer: 11 Dez. 2007 → 14 Dez. 2007

Publikationsreihe

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Abstract

This paper presents a scalable massively parallel CRC architecture for high-speed network processing. The proposed method considers wide data busses, which result in highest throughput. In addition, data streams are processed without interrupts. An investigated 65nm-ASIC implementation example for 32-bit CRC encoding operates on 58 GBps data streams at reasonable costs (0.036 mm 2). The proposed method can be exploited furthermore in order to develop a configurable circuit for a group of generator polynomials, without the requirement of fully programmable architecture.

ASJC Scopus Sachgebiete

Zitieren

On the design of scalable massively parallel CRC circuits. / Septinus, Konstantin; Le, Thuyen; Mayer, Ulrich et al.
ICECS 2007 : 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. S. 142-145 4510950 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

Septinus, K, Le, T, Mayer, U & Pirsch, P 2007, On the design of scalable massively parallel CRC circuits. in ICECS 2007 : 14th IEEE International Conference on Electronics, Circuits and Systems., 4510950, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, S. 142-145, 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007, Marrakech, Marokko, 11 Dez. 2007. https://doi.org/10.1109/ICECS.2007.4510950
Septinus, K., Le, T., Mayer, U., & Pirsch, P. (2007). On the design of scalable massively parallel CRC circuits. In ICECS 2007 : 14th IEEE International Conference on Electronics, Circuits and Systems (S. 142-145). Artikel 4510950 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.2007.4510950
Septinus K, Le T, Mayer U, Pirsch P. On the design of scalable massively parallel CRC circuits. in ICECS 2007 : 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. S. 142-145. 4510950. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2007.4510950
Septinus, Konstantin ; Le, Thuyen ; Mayer, Ulrich et al. / On the design of scalable massively parallel CRC circuits. ICECS 2007 : 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. S. 142-145 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).
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