Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 2023 IEEE 13th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2023 |
| Herausgeber (Verlag) | IEEE Computer Society |
| Seiten | 94-99 |
| Seitenumfang | 6 |
| ISBN (elektronisch) | 9798350324150 |
| Publikationsstatus | Veröffentlicht - 2023 |
| Veranstaltung | 13th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2023 - Berlin, Deutschland Dauer: 4 Sept. 2022 → 5 Sept. 2022 |
Publikationsreihe
| Name | IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin |
|---|---|
| ISSN (Print) | 2166-6814 |
| ISSN (elektronisch) | 2166-6822 |
Abstract
Convolutional neural networks (CNNs) have been demonstrated to be a successful approach in the field of artificial intelligence (AI). Deploying CNNs on embedded devices at a large scale would contribute significantly to the advancement and practical implementation of AI in various industries. However, the complexity of CNNs in terms of memory and operation requirements poses challenges in terms of computing performance, memory bandwidth, and flexibility of the executing hardware. This paper introduces a framework that addresses these issues through model quantization and hardware acceleration on a scalable vertical vector processor architecture. Firstly, the framework includes a method for layer fusion, which is designed to optimize the hardware utilization. Secondly, data storage is optimized to enhance memory efficiency. Lastly, CNNs are mapped onto the vertical vector processing concept of the hardware accelerator. The effectiveness of the proposed framework is evaluated by analyzing the accelerator efficiency based on a field-programmable gate array (FPGA). The results demonstrate that the framework offers flexibility, configurability, and efficient mapping for typical CNN implementations. The framework achieves up to 84% of the peak performance of the vector processor for the VGG net.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
- Ingenieurwesen (insg.)
- Wirtschaftsingenieurwesen und Fertigungstechnik
- Ingenieurwesen (insg.)
- Medientechnik
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- BibTex
- RIS
2023 IEEE 13th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2023. IEEE Computer Society, 2023. S. 94-99 (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - N2V2PRO
T2 - 13th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2023
AU - Gesper, Sven
AU - Thieu, Gia Bao
AU - Kohler, Daniel
AU - Kock, Markus
AU - Berthold, Tim
AU - Renke, Oliver
AU - Blume, Holger
AU - Paya-Vaya, Guillermo
N1 - Funding information: Acknowledgment This work was partly funded by the German Federal Ministry of Education and Research (BMBF) under project number 16ME0379 (ZuSE-KI-AVF).
PY - 2023
Y1 - 2023
N2 - Convolutional neural networks (CNNs) have been demonstrated to be a successful approach in the field of artificial intelligence (AI). Deploying CNNs on embedded devices at a large scale would contribute significantly to the advancement and practical implementation of AI in various industries. However, the complexity of CNNs in terms of memory and operation requirements poses challenges in terms of computing performance, memory bandwidth, and flexibility of the executing hardware. This paper introduces a framework that addresses these issues through model quantization and hardware acceleration on a scalable vertical vector processor architecture. Firstly, the framework includes a method for layer fusion, which is designed to optimize the hardware utilization. Secondly, data storage is optimized to enhance memory efficiency. Lastly, CNNs are mapped onto the vertical vector processing concept of the hardware accelerator. The effectiveness of the proposed framework is evaluated by analyzing the accelerator efficiency based on a field-programmable gate array (FPGA). The results demonstrate that the framework offers flexibility, configurability, and efficient mapping for typical CNN implementations. The framework achieves up to 84% of the peak performance of the vector processor for the VGG net.
AB - Convolutional neural networks (CNNs) have been demonstrated to be a successful approach in the field of artificial intelligence (AI). Deploying CNNs on embedded devices at a large scale would contribute significantly to the advancement and practical implementation of AI in various industries. However, the complexity of CNNs in terms of memory and operation requirements poses challenges in terms of computing performance, memory bandwidth, and flexibility of the executing hardware. This paper introduces a framework that addresses these issues through model quantization and hardware acceleration on a scalable vertical vector processor architecture. Firstly, the framework includes a method for layer fusion, which is designed to optimize the hardware utilization. Secondly, data storage is optimized to enhance memory efficiency. Lastly, CNNs are mapped onto the vertical vector processing concept of the hardware accelerator. The effectiveness of the proposed framework is evaluated by analyzing the accelerator efficiency based on a field-programmable gate array (FPGA). The results demonstrate that the framework offers flexibility, configurability, and efficient mapping for typical CNN implementations. The framework achieves up to 84% of the peak performance of the vector processor for the VGG net.
KW - CNN Layer Conversion
KW - Custom Accelerator
KW - Neural Network Hardware Mapping
KW - Neural Network Quantization
UR - http://www.scopus.com/inward/record.url?scp=85182920276&partnerID=8YFLogxK
U2 - 10.1109/icce-berlin58801.2023.10375652
DO - 10.1109/icce-berlin58801.2023.10375652
M3 - Conference contribution
AN - SCOPUS:85182920276
T3 - IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin
SP - 94
EP - 99
BT - 2023 IEEE 13th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2023
PB - IEEE Computer Society
Y2 - 4 September 2022 through 5 September 2022
ER -