Details
| Originalsprache | Englisch |
|---|---|
| Aufsatznummer | IP-P5 |
| Seiten (von - bis) | 127-130 |
| Seitenumfang | 4 |
| Fachzeitschrift | Proceedings of the International Symposium on Power Semiconductor Devices and ICs |
| Publikationsstatus | Veröffentlicht - 2005 |
| Veranstaltung | 17th International Symposium on Power Semiconductor Devices and ICs, ISPSD'05 - Sanata Barbara, CA, USA / Vereinigte Staaten Dauer: 23 Mai 2005 → 26 Mai 2005 |
Abstract
Switching of power stages in smart power ICs, which drive an inductive load, turns on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. We present a new parasitic transistor model for post layout simulation, which accounts for a strongly inhomogeneous current flow, a base width of up to a few hundred μm, multiple base contacts and collectors, and whose parameters are easily extractable from layout and technology data.
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in: Proceedings of the International Symposium on Power Semiconductor Devices and ICs, 2005, S. 127-130.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Modeling substrate currents in smart power ICs
AU - Oehmen, Joerg
AU - Olbrich, Markus
AU - Barke, Erich
PY - 2005
Y1 - 2005
N2 - Switching of power stages in smart power ICs, which drive an inductive load, turns on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. We present a new parasitic transistor model for post layout simulation, which accounts for a strongly inhomogeneous current flow, a base width of up to a few hundred μm, multiple base contacts and collectors, and whose parameters are easily extractable from layout and technology data.
AB - Switching of power stages in smart power ICs, which drive an inductive load, turns on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. We present a new parasitic transistor model for post layout simulation, which accounts for a strongly inhomogeneous current flow, a base width of up to a few hundred μm, multiple base contacts and collectors, and whose parameters are easily extractable from layout and technology data.
UR - http://www.scopus.com/inward/record.url?scp=27744541928&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:27744541928
SP - 127
EP - 130
JO - Proceedings of the International Symposium on Power Semiconductor Devices and ICs
JF - Proceedings of the International Symposium on Power Semiconductor Devices and ICs
SN - 1063-6854
M1 - IP-P5
T2 - 17th International Symposium on Power Semiconductor Devices and ICs, ISPSD'05
Y2 - 23 May 2005 through 26 May 2005
ER -